公开(公告)号：US20160358820A1

公开(公告)日：2016-12-08

申请号：US15239178

申请日：2016-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US20140363969A1

公开(公告)日：2014-12-11

申请号：US13913823

申请日：2013-06-10

Applicant: Globalfoundries Inc. ,  International Business Machines Corporation

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Yunpeng Yin ,  Ailian Zhao

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898

Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

Abstract translation: 一种包括在衬底上形成五层硬掩模的方法，所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中，产生第一通孔图案，第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在 双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中，从而产生自对准的通孔，所述自对准通孔打开通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。

公开(公告)号：US10157789B2

公开(公告)日：2018-12-18

申请号：US15239178

申请日：2016-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

公开(公告)号：US20160336225A1

公开(公告)日：2016-11-17

申请号：US14710894

申请日：2015-05-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US09330965B2

公开(公告)日：2016-05-03

申请号：US14837827

申请日：2015-08-27

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Yunpeng Yin ,  Ailian Zhao

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898

Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

公开(公告)号：US09219007B2

公开(公告)日：2015-12-22

申请号：US13913823

申请日：2013-06-10

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Yunpeng Yin ,  Ailian Zhao

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898

Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

Abstract translation: 一种包括在衬底上形成五层硬掩模的方法，所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中，产生第一通孔图案，第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在 双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中，从而产生自对准的通孔，所述自对准通孔开口通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。

公开(公告)号：US20200004155A1

公开(公告)日：2020-01-02

申请号：US16022752

申请日：2018-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yong Liang ,  Lei Sun ,  Yongan Xu ,  Craig D. Higgins

IPC: G03F7/20 ,  G03F1/22

Abstract: Disclosed are embodiments of a multi-layer stack and photolithography methods and systems that employ such a stack. The disclosed multi-layer stacks include a photoresist layer on an underlayer. The photoresist layer and underlayer are made of different materials, which are selected so that valence and conduction band offsets between the underlayer and photoresist layer create an effective electric field (i.e., so that the stack is “self-biased”). When areas of the photoresist layer are exposed to radiation during photolithography and the radiation passes through photoresist layer and excites electrons in the underlayer, this effective electric field facilitates movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer in a direction normal to the interface between the underlayer and the photoresist layer. Movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer improves photoresist layer development and pattern resolution.

公开(公告)号：US09984919B1

公开(公告)日：2018-05-29

申请号：US15664584

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Yongan Xu ,  Peng Xu ,  Yann Mignot

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76807 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53295

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first section of a mandrel is covered with a feature of an etch mask. A top surface of a second section of the mandrel is exposed by the feature of the etch mask and is recessed with an etching process. A conductive via is formed that reproduces a shape of the first section of the mandrel, and a conductive line is formed that reproduces a shape of the second section of the mandrel. The mandrel is removed to release the conductive via and the conductive line.

公开(公告)号：US20150371896A1

公开(公告)日：2015-12-24

申请号：US14837827

申请日：2015-08-27

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Yunpeng Yin ,  Ailian Zhao

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898

Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

Abstract translation: 一种包括在衬底上形成五层硬掩模的方法，所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中，产生第一通孔图案，第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在 双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中，从而产生自对准的通孔，所述自对准通孔开口通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。

公开(公告)号：US10782606B2

公开(公告)日：2020-09-22

申请号：US16022752

申请日：2018-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yong Liang ,  Lei Sun ,  Yongan Xu ,  Craig D. Higgins

IPC: G03F1/22 ,  G03F7/20

Abstract: Disclosed are embodiments of a multi-layer stack and photolithography methods and systems that employ such a stack. The disclosed multi-layer stacks include a photoresist layer on an underlayer. The photoresist layer and underlayer are made of different materials, which are selected so that valence and conduction band offsets between the underlayer and photoresist layer create an effective electric field (i.e., so that the stack is “self-biased”). When areas of the photoresist layer are exposed to radiation during photolithography and the radiation passes through photoresist layer and excites electrons in the underlayer, this effective electric field facilitates movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer in a direction normal to the interface between the underlayer and the photoresist layer. Movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer improves photoresist layer development and pattern resolution.