公开(公告)号：US09984919B1

公开(公告)日：2018-05-29

申请号：US15664584

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Yongan Xu ,  Peng Xu ,  Yann Mignot

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76807 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53295

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first section of a mandrel is covered with a feature of an etch mask. A top surface of a second section of the mandrel is exposed by the feature of the etch mask and is recessed with an etching process. A conductive via is formed that reproduces a shape of the first section of the mandrel, and a conductive line is formed that reproduces a shape of the second section of the mandrel. The mandrel is removed to release the conductive via and the conductive line.

公开(公告)号：US09601366B2

公开(公告)日：2017-03-21

申请号：US14810143

申请日：2015-07-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie ,  Peng Xu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L21/3213

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/60 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78

Abstract: A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

公开(公告)号：US20170033196A1

公开(公告)日：2017-02-02

申请号：US15282836

申请日：2016-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie ,  Peng Xu

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/027

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/60 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78

Abstract: A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

Abstract translation: 一种用于形成栅极切割区域的方法包括通过形成在衬底上的硬掩模，虚设层和虚设电介质形成锥形轮廓栅极线沟槽，在沟槽中形成虚拟栅极电介质和虚拟栅极导体并平面化顶部 表面达到硬面膜。 虚拟栅极导体被图案化以在切割区域中形成切割沟槽。 虚拟栅极导体是凹进的，并且切割沟槽填充有第一介电材料。 去除虚设层并形成间隔物。 栅极线被打开，并且虚拟栅极导体从栅极线沟槽移除。 沉积栅介质和导体，并且栅极盖层提供耦合到切割沟槽中的第一电介质材料以形成切割最后结构的第二电介质。

公开(公告)号：US10068804B2

公开(公告)日：2018-09-04

申请号：US15423326

申请日：2017-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Peng Xu ,  Chun Wing Yeung

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/321 ,  H01L29/08 ,  H01L29/417 ,  H01L21/66

CPC classification number: H01L21/823431 ,  H01L21/823425 ,  H01L22/12 ,  H01L22/20 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method and system are disclosed herein for an adjustable effective fin height in a gate region of a finFET device. Fin structures, each having a first height, a fin, an oxide liner, and a nitride liner, are formed. A first portion of the nitride liner is removed. A first portion of the oxide liner is removed. A second portion of the nitride liner in a gate portion of the finFET. Source/drain(s) are formed, and a nitride spacer between the source/drain and the gate portion is formed. A second portion of the oxide liner is exposed by removing the second portion of the nitride liner, exposing a second portion of the fin, wherein the first and second exposed portions of the fin being an effective fin height in the gate portion.

公开(公告)号：US20180218947A1

公开(公告)日：2018-08-02

申请号：US15423326

申请日：2017-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Peng Xu ,  Chun Wing Yeung

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/321 ,  H01L29/08 ,  H01L29/417 ,  H01L21/66

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L22/20 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545

Abstract: A method and system are disclosed herein for an adjustable effective fin height in a gate region of a finFET device. Fin structures, each having a first height, a fin, an oxide liner, and a nitride liner, are formed. A first portion of the nitride liner is removed. A first portion of the oxide liner is removed. A second portion of the nitride liner in a gate portion of the finFET. Source/drain(s) are formed, and a nitride spacer between the source/drain and the gate portion is formed. A second portion of the oxide liner is exposed by removing the second portion of the nitride liner, exposing a second portion of the fin, wherein the first and second exposed portions of the fin being an effective fin height in the gate portion.

公开(公告)号：US20170033000A1

公开(公告)日：2017-02-02

申请号：US14810143

申请日：2015-07-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie ,  Peng Xu

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/60 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78

Abstract: A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

公开(公告)号：US09601335B2

公开(公告)日：2017-03-21

申请号：US15282836

申请日：2016-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie ,  Peng Xu

IPC: H01L21/28 ,  H01L23/60 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/60 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78

Abstract: A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.