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    RAISED FIN STRUCTURES AND METHODS OF FABRICATION
    1.
    发明申请
    RAISED FIN STRUCTURES AND METHODS OF FABRICATION 有权
    提高精细结构和制造方法

    公开(公告)号：US20150372084A1

    公开(公告)日：2015-12-24

    申请号：US14309956

    申请日：2014-06-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yi QI ,  Xunyuan ZHANG ,  Catherine B. LABELLE

    IPC: H01L29/06 ,  H01L21/02 ,  H01L21/311

    CPC classification number: H01L21/02532 ,  H01L21/02639 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

    Abstract translation: 提供一种制造凸起翅片结构的方法，所述制造方法包括：在衬底上提供衬底和至少一个电介质层; 在所述至少一个电介质层中形成沟槽，所述沟槽具有下部，侧部和上部，所述上部至少部分地从所述下部向外偏移并且通过所述侧部与所述下部 一部分; 并且在沟槽中生长材料以形成凸起的翅片结构，其中形成沟槽以确保沟槽的下部中的任何生长缺陷终止于沟槽的下部或横向部分，并且不延伸 进入沟槽的上部。

    DUAL-STRAINED NANOWIRE AND FINFET DEVICES WITH DIELECTRIC ISOLATION
    3.
    发明申请
    DUAL-STRAINED NANOWIRE AND FINFET DEVICES WITH DIELECTRIC ISOLATION 有权
    具有介电隔离的双应变纳米线和FinFET器件

    公开(公告)号：US20160104799A1

    公开(公告)日：2016-04-14

    申请号：US14511715

    申请日：2014-10-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yi QI ,  Catherine B. LABELLE ,  Xiuyu CAI

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L29/775

    CPC classification number: H01L29/7849 ,  B82Y10/00 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/775

    Abstract: A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions.

    Abstract translation: 提供具有绝缘隔离的双应变Si和SiGe FinFET器件和双应变纳米线器件及其形成方法。 实施例包括形成在硅衬底上的SiGe SRB，SRB具有第一区域和第二区域; 分别形成在SiGe SRB的第一区域和第二区域上的第一和第二介电隔离层; 形成在第一介电隔离层上的拉伸应变Si翅片; 形成在所述第二介电隔离层上的压缩应变SiGe鳍; 形成在拉伸应变Si翅片的相对侧的第一源极/漏极区域; 形成在压缩应变SiGe翅片的相对侧的第二源极/漏极区域; 形成在第一源/漏区之间的第一RMG; 以及形成在第二源/漏区之间的第二RMG。

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