公开(公告)号：US09435947B2

公开(公告)日：2016-09-06

申请号：US14850381

申请日：2015-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol T. Ryan

IPC: G02B6/12 ,  G02F1/025 ,  H01L21/76 ,  H01L23/52 ,  H01L27/06 ,  H01L21/768 ,  H01L23/48 ,  G02B6/43 ,  G02B6/122 ,  H01L23/367 ,  H01L23/373 ,  H01L23/528 ,  H01L23/532 ,  H01L27/12

CPC classification number: G02B6/12004 ,  G02B6/122 ,  G02B6/43 ,  G02F1/025 ,  H01L21/76877 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0694 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first substrate layer, the optical component being connected to the transistor.

Abstract translation: 公开了使IC中的光学部件集成的结果和所得到的器件的方法。 实施例包括：通过绝缘体层提供与第二衬底水平分离的IC的第一衬底层; 在所述第二基板层上提供晶体管; 以及在所述第一衬底层上提供光学部件，所述光学部件连接到所述晶体管。

公开(公告)号：US20130241062A1

公开(公告)日：2013-09-19

申请号：US13849415

申请日：2013-03-22

Applicant: GLOBALFOUNDRIES INC

Inventor： Errol T. Ryan ,  Xunyuan Zhang

IPC: H01L23/535

CPC classification number: H01L23/535 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.

Abstract translation: 提供集成电路，用于凹入衬底内的嵌入式铜特征的工艺，以及用于使集成电路的层间电介质衬底内的嵌入式铜互连凹陷的工艺。 在一个实施例中，在诸如层间电介质基板的衬底内嵌入诸如嵌入式铜互连的嵌入式铜特征的方法包括提供其中布置有嵌入式铜特征的衬底。 嵌入的铜特征具有暴露的表面，并且衬底具有与嵌入的铜特征的暴露表面相邻的衬底表面。 嵌入的铜特征的暴露表面被氮化以在嵌入的铜特征中形成一层氮化铜。 从嵌入的铜特征中选择性地蚀刻氮化铜以将嵌入的铜特征凹入到衬底内。

公开(公告)号：US20140145332A1

公开(公告)日：2014-05-29

申请号：US13684871

申请日：2012-11-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Errol T. Ryan ,  Zoran Krivokapic ,  Xunyuan Zhang ,  Christian Witt ,  Ming He ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a graphene liner layer in at least the trench/via, forming a copper-based seed layer on the graphene liner layer, depositing a bulk copper-based material on the copper-based seed layer so as to overfill the trench/via, and performing at least one chemical mechanical polishing process to remove at least excess amounts of the bulk copper-based material and the copper-based seed layer positioned outside of the trench/via to thereby define a copper-based conductive structure with a graphene liner layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在至少沟槽/通孔中形成石墨烯衬里层，在石墨烯衬层上形成铜基晶种层，沉积大量基于铜的 在铜基种子层上的材料，以便过度填充沟槽/通孔，并进行至少一种化学机械抛光工艺以去除至少过量的大量铜基材料和位于外部的铜基种子层 沟槽/通孔，从而限定铜基导电结构，其中石墨烯衬里层位于铜基导电结构和绝缘材料层之间。

公开(公告)号：US08704372B2

公开(公告)日：2014-04-22

申请号：US13849415

申请日：2013-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol T. Ryan ,  Xunyuan Zhang

IPC: H01L23/48

CPC classification number: H01L23/535 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.

Abstract translation: 提供集成电路，用于凹入衬底内的嵌入式铜特征的工艺，以及用于使集成电路的层间电介质衬底内的嵌入式铜互连凹陷的工艺。 在一个实施例中，在诸如层间电介质基板的衬底内嵌入诸如嵌入式铜互连的嵌入式铜特征的方法包括提供其中布置有嵌入式铜特征的衬底。 嵌入的铜特征具有暴露的表面，并且衬底具有与嵌入的铜特征的暴露表面相邻的衬底表面。 嵌入的铜特征的暴露表面被氮化以在嵌入的铜特征中形成一层氮化铜。 从嵌入的铜特征中选择性地蚀刻氮化铜以将嵌入的铜特征凹入到衬底内。