公开(公告)号：US10332969B2

公开(公告)日：2019-06-25

申请号：US16167081

申请日：2018-10-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.

公开(公告)号：US09663346B1

公开(公告)日：2017-05-30

申请号：US15046245

申请日：2016-02-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bichoy Bahr ,  Zoran Krivokapic

IPC: H03B1/00 ,  H03K3/00 ,  B81B3/00 ,  H03H3/007 ,  H03H9/24 ,  H01L29/78

CPC classification number: B81B3/0021 ,  B81B2201/0271 ,  H01L29/785 ,  H03H9/2405 ,  H03H2009/02314

Abstract: A semiconductor structure includes a semiconductor substrate, fins coupled to the semiconductor substrate, FinFETs on the fins, a common gate for the FinFETs, a dielectric layer on the semiconductor substrate, the dielectric layer surrounding a cavity with the semiconductor substrate providing bottom confinement of the acoustic cavity by total internal reflection, and an interconnect structure above the FinFETs, the interconnect structure including phononic crystal(s) to confine acoustic energy in the cavity including the cavity and metal layer(s) sandwiched between two dielectric layers. The semiconductor structure may be realized, during FEOL fabrication of a FinFET, by forming a cavity on a surface of a semiconductor substrate. Then, after fabrication of the FinFET, forming an interconnect structure for the FinFET. During formation of the interconnect structure, materials of the interconnect structure are used to form a phononic crystal to confine the cavity between the phononic crystal and the semiconductor substrate.

公开(公告)号：US20150162435A1

公开(公告)日：2015-06-11

申请号：US14100196

申请日：2013-12-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bhagawan Sahu ,  Zoran Krivokapic

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/165 ,  H01L29/66795

Abstract: Approaches for providing asymmetrical channel growth of a cladding layer over fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, in one approach, a FinFET device comprises a set of fins formed from a substrate, a shallow trench isolation layer formed adjacent each of the set of fins, and a cladding layer (e.g., silicon germanium) formed over each of the set of fins, wherein a thickness of the cladding layer atop each of the set of fins is greater than a thickness of the cladding layer along each sidewall of the set of fins. In one embodiment, the thickness of the cladding layer atop the set of fins is approximately two times (2×) greater than the thickness of the cladding layer along each sidewall of the set of fins.

Abstract translation: 公开了一种用于在翅片场效应晶体管（FinFET）器件的鳍片上提供包覆层的不对称沟道生长的方法。 具体地说，在一种方法中，FinFET器件包括由衬底形成的一组翅片，与该组翅片相邻形成的浅沟槽隔离层，以及形成在该组翅片之上的覆层（例如，硅锗） 翅片，其中在所述一组翅片中的每一个上方的所述包覆层的厚度大于所述一组翅片的每个侧壁处的所述包覆层的厚度。 在一个实施例中，覆盖层顶部的散热片的厚度比沿着该组散热片的每个侧壁的包覆层的厚度大大约两倍（2×）。

公开(公告)号：US20140312434A1

公开(公告)日：2014-10-23

申请号：US14328275

申请日：2014-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zoran Krivokapic ,  Bhagawan Sahu

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/51 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02628 ,  H01L21/02664 ,  H01L29/4966 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

公开(公告)号：US10002859B1

公开(公告)日：2018-06-19

申请号：US15632909

申请日：2017-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bichoy Bahr ,  Zoran Krivokapic

IPC: H01L27/02 ,  H01L27/098 ,  H01L23/532

CPC classification number: H01L27/0203 ,  H01L23/53214 ,  H01L23/53228 ,  H01L27/098 ,  H01L29/785 ,  H03H9/2405 ,  H03H2009/02314

Abstract: Circuit structures including a FinFET resonant body transistor are disclosed. One circuit structure includes: a plurality of fins over a substrate and a plurality of gate structures over the plurality of fins, the plurality of gate structures including at least one voltage sensing gate and multiple driving junction gates disposed on opposing sides of the at least one voltage sensing gate; at least one phononic crystal, wherein the at least one phononic crystal is arranged to confine vibrational energy arising from electrically induced mechanical stresses in the fins disposed below the driving junction gates; and, wherein the electrically induced mechanical stresses modulate carrier mobility in the at least one voltage sensing gate to produce a current extractable by the circuit structure.

公开(公告)号：US09685529B1

公开(公告)日：2017-06-20

申请号：US15189476

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Deepak Nayak ,  Zoran Krivokapic ,  Srinivasa Banna

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532

CPC classification number: H01L29/66522 ,  H01L21/76867 ,  H01L23/53271 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods for creating barrier layers in a III-V electron channel to reduce band-to-band leakage current and the resulting devices are disclosed. Embodiments include forming a fin channel portion comprising a III-V material, on a barrier layer; forming undoped InP semiconductor spacers at opposite ends of the fin channel portion on the barrier layer; forming S/D regions adjacent the undoped InP semiconductor spacers on the barrier layer; and forming a high-k/metal gate over the fin channel portion and undoped InP semiconductor spacers.

公开(公告)号：US20140145332A1

公开(公告)日：2014-05-29

申请号：US13684871

申请日：2012-11-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Errol T. Ryan ,  Zoran Krivokapic ,  Xunyuan Zhang ,  Christian Witt ,  Ming He ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a graphene liner layer in at least the trench/via, forming a copper-based seed layer on the graphene liner layer, depositing a bulk copper-based material on the copper-based seed layer so as to overfill the trench/via, and performing at least one chemical mechanical polishing process to remove at least excess amounts of the bulk copper-based material and the copper-based seed layer positioned outside of the trench/via to thereby define a copper-based conductive structure with a graphene liner layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在至少沟槽/通孔中形成石墨烯衬里层，在石墨烯衬层上形成铜基晶种层，沉积大量基于铜的 在铜基种子层上的材料，以便过度填充沟槽/通孔，并进行至少一种化学机械抛光工艺以去除至少过量的大量铜基材料和位于外部的铜基种子层 沟槽/通孔，从而限定铜基导电结构，其中石墨烯衬里层位于铜基导电结构和绝缘材料层之间。

公开(公告)号：US09899363B1

公开(公告)日：2018-02-20

申请号：US15632927

申请日：2017-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bichoy Bahr ,  Zoran Krivokapic

IPC: H01L27/02 ,  H01L27/098 ,  H01L23/532

CPC classification number: H01L27/0203 ,  H01L23/53214 ,  H01L23/53228 ,  H01L27/098 ,  H03H3/0072 ,  H03H9/2405 ,  H03H2009/02314

Abstract: Circuit structures including a FinFET resonant body transistor are disclosed. One circuit structure includes: a plurality of fins over a substrate and a plurality of gate structures over the plurality of fins, the plurality of gate structures comprising at least one voltage sensing gate, and at least two of the plurality of fins comprising multiple pn-junctions disposed on opposing sides of the at least one voltage sensing gate, the multiple pn-junctions being fabricated to operate as driving units; at least one phononic crystal, wherein the at least one phononic crystal is arranged to confine vibrational energy arising from electrically induced mechanical stresses in the fins comprising driving units; and, wherein the electrically induced mechanical stresses modulate carrier mobility in the at least one voltage sensing gate to produce a current extractable by the circuit structure.

公开(公告)号：US10141414B1

公开(公告)日：2018-11-27

申请号：US15784500

申请日：2017-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/78

Abstract: A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When forming the negative capacitor portion, the value of the negative capacitance may be adjusted on the basis of two different mechanisms or manufacturing processes, thereby providing superior matching of the positive floating gate electrode portion and the negative capacitor portion. For example, the layer thickness of the ferroelectric material and the effective capacitive area of the dielectric material may be adjusted on the basis of independent manufacturing processes.

公开(公告)号：US09997695B2

公开(公告)日：2018-06-12

申请号：US15458316

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zoran Krivokapic ,  Bichoy Bahr

IPC: H01L29/84 ,  H01L41/107 ,  H01L41/047 ,  H01L41/29 ,  H01L29/78

CPC classification number: H01L41/107 ,  H01L29/78391 ,  H01L29/84 ,  H01L41/0474 ,  H01L41/29

Abstract: Methods to utilize piezoelectric materials as a gate dielectric in RBTs in an IC device to generate and sense higher frequency signals with high Qs and resulting devices are disclosed. Embodiments include forming, on an upper surface of a semiconductor layer, RBTs comprising even multiples of sensing RBTs and driving RBTs, each RBT including a piezoelectric gate dielectric layer, a gate, and a dielectric spacer on opposite sides of the piezoelectric gate dielectric layer and gate, wherein at least one pair of sensing RBTs is directly between two groups of driving RBTs; forming metal layers, separated by interlayer dielectric layers, above the RBTs; and forming vias through a dielectric layer above the RBTs connecting the RBTs to a metal layer.