公开(公告)号：US20140242788A1

公开(公告)日：2014-08-28

申请号：US13775416

申请日：2013-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gabriela Dilliway ,  Dina Triyoso ,  Elke Erben ,  Rimoon Agaiby

IPC: H01L21/28

CPC classification number: H01L21/28255 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66651

Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

Abstract translation: 本文公开的一种说明性方法包括在小于400℃的温度下进行原子层沉积（ALD）工艺，以在半导体材料的含锗区域上沉积二氧化硅层并形成晶体管器件的栅极结构 在二氧化硅层之上。

公开(公告)号：US20140117417A1

公开(公告)日：2014-05-01

申请号：US13661188

申请日：2012-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： El Mehdi Bazizi ,  Alban Zaka ,  Gabriela Dilliway ,  Bo Bai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

Abstract translation: 在复杂的半导体器件中，可以通过使用嵌入式应变诱导半导体合金，在有效的应变诱导机制的基础上形成晶体管。 应变诱导半导体材料可以被提供为具有平滑应变转移到相邻沟道区域中的渐变材料，以便减少晶格缺陷的数量并且提供增强的应变条件，这进而直接转化为优异的晶体管性能。 分级应变诱导半导体材料的优越结构可以通过在选择性外延生长工艺期间选择合适的工艺参数而不造成额外的工艺复杂性来实现。

公开(公告)号：US10109492B2

公开(公告)日：2018-10-23

申请号：US13775416

申请日：2013-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gabriela Dilliway ,  Dina Triyoso ,  Elke Erben ,  Rimoon Agaiby

IPC: H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

公开(公告)号：US20160064286A1

公开(公告)日：2016-03-03

申请号：US14476031

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gabriela Dilliway ,  Bo Bai ,  Peter Javorka ,  Dina H. Triyoso

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092

Abstract: Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit is provided. The method includes providing a semiconductor substrate with a first gate structure and a second gate structure and a shallow trench isolation region outside of the first and second gate structures, depositing a mask on the first gate structure, and depositing a protection layer on the shallow trench isolation region to embed a STI protective cap.

Abstract translation: 提供了制造集成电路及其部件的方法。 根据示例性实施例，提供了一种用于制造集成电路的方法。 该方法包括在第一和第二栅极结构之外提供具有第一栅极结构和第二栅极结构以及浅沟槽隔离区域的半导体衬底，在第一栅极结构上沉积掩模，以及在浅沟槽上沉积保护层 隔离区域嵌入STI保护帽。

公开(公告)号：US08853752B2

公开(公告)日：2014-10-07

申请号：US13661188

申请日：2012-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： El Mehdi Bazizi ,  Alban Zaka ,  Gabriela Dilliway ,  Bo Bai

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

Abstract translation: 在复杂的半导体器件中，可以通过使用嵌入式应变诱导半导体合金，在有效的应变诱导机制的基础上形成晶体管。 应变诱导半导体材料可以被提供为具有平滑应变转移到相邻沟道区域中的渐变材料，以便减少晶格缺陷的数量并且提供增强的应变条件，这进而直接转化为优异的晶体管性能。 分级应变诱导半导体材料的优越结构可以通过在选择性外延生长工艺期间选择合适的工艺参数而不造成额外的工艺复杂性来实现。