公开(公告)号：US20140242788A1

公开(公告)日：2014-08-28

申请号：US13775416

申请日：2013-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gabriela Dilliway ,  Dina Triyoso ,  Elke Erben ,  Rimoon Agaiby

IPC: H01L21/28

CPC classification number: H01L21/28255 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66651

Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

Abstract translation: 本文公开的一种说明性方法包括在小于400℃的温度下进行原子层沉积（ALD）工艺，以在半导体材料的含锗区域上沉积二氧化硅层并形成晶体管器件的栅极结构 在二氧化硅层之上。

公开(公告)号：US20180158835A1

公开(公告)日：2018-06-07

申请号：US15366425

申请日：2016-12-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Thomas Melde ,  Elke Erben

IPC: H01L27/11568 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L27/11573 ,  H01L21/033 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/11568 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/0332 ,  H01L21/28185 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/518

Abstract: Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.

公开(公告)号：US10079242B2

公开(公告)日：2018-09-18

申请号：US15366425

申请日：2016-12-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Thomas Melde ,  Elke Erben

IPC: H01L29/10 ,  H01L27/11568 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L27/11573 ,  H01L21/033 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/11568 ,  H01L21/84 ,  H01L27/11573 ,  H01L27/1203 ,  H01L27/1237 ,  H01L29/0649 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7841 ,  H01L29/78654 ,  H01L29/78684 ,  H01L2029/42388

Abstract: Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.

公开(公告)号：US20150162414A1

公开(公告)日：2015-06-11

申请号：US14097338

申请日：2013-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Elke Erben

IPC: H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7833

Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 所要求保护的方法提出了通过在金属栅极层和栅极半导体材料之间形成包括附加金属层的栅极结构而实现的改进的全硅化栅。 然后可以优化硅化工艺，以便形成包含附加金属层的金属和形成与下金属硅化物层的界面的上金属硅化物层的下金属硅化物层。

公开(公告)号：US10109492B2

公开(公告)日：2018-10-23

申请号：US13775416

申请日：2013-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gabriela Dilliway ,  Dina Triyoso ,  Elke Erben ,  Rimoon Agaiby

IPC: H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

公开(公告)号：US09236440B2

公开(公告)日：2016-01-12

申请号：US14097338

申请日：2013-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Elke Erben

IPC: H01L21/44 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7833

Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 所要求保护的方法提出了通过在金属栅极层和栅极半导体材料之间形成包括附加金属层的栅极结构而实现的改进的全硅化栅。 然后可以优化硅化工艺，以便形成包含附加金属层的金属和形成与下金属硅化物层的界面的上金属硅化物层的下金属硅化物层。

公开(公告)号：US20130280873A1

公开(公告)日：2013-10-24

申请号：US13793401

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Elke Erben ,  Martin Trentzsch ,  Richard Carter ,  Carsten Grass

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02181 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/28079 ,  H01L21/28194 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477

Abstract: When forming sophisticated circuit elements, such as transistors, capacitors and the like, using a combination of a conventional dielectric material and a high-k dielectric material, superior performance and reliability may be achieved by forming a hafnium oxide-based high-k dielectric material on a conventional dielectric layer with a preceding surface treatment, for instance using APM at room temperature. In this manner, sophisticated transistors of superior performance and with improved uniformity of threshold voltage characteristics may be obtained, while also premature failure due to dielectric breakdown, hot carrier injection and the like may be reduced.

Abstract translation: 当形成诸如晶体管，电容器等的复杂电路元件时，通过使用常规电介质材料和高k电介质材料的组合，可以通过形成基于氧化铪的高k电介质材料来实现优异的性能和可靠性 在具有前面表面处理的常规电介质层上，例如在室温下使用APM。 以这种方式，可以获得具有优异性能并具有改善的阈值电压特性均匀性的复杂晶体管，同时由于介电击穿，热载流子注入等而导致的过早故障也可能被降低。