公开(公告)号：US09947545B2

公开(公告)日：2018-04-17

申请号：US15437837

申请日：2017-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Jiong Li

IPC: H01L21/336 ,  H01L21/283 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/283 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/32139 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/513

Abstract: Methods for forming a gate structure of a circuit structure are provide. The methods for forming the gate structure may include: forming a first gate pattern in a gate mask layer, the forming including a first etching of rounded corner portions of the first gate pattern; forming a second gate pattern in the gate mask layer, the second gate pattern at least partially overlapping the first gate pattern, the forming including a second etching of rounded corner portions of the second gate pattern; and, etching the gate mask layer using the first gate pattern and second gate pattern to form the gate structure.

公开(公告)号：US20160300754A1

公开(公告)日：2016-10-13

申请号：US14684949

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Deniz Elizabeth Civay ,  Jason Eugene Stephens ,  Jiong Li ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76811 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract translation: 提供了制造集成电路的方法。 一种方法包括分解用于半导体器件层的主图案布局，该半导体器件层包括目标金属线，目标金属线与目标互连通孔/触点成为第一子图案和第二子图案。 目标金属线被分解为作为第一子图案的一部分的第一线特征图案和作为第二子图案的一部分的第二线特征图案，使得第一和第二线特征图案具有限定 对应于目标互连通孔/触点的针迹。 生成对应于第一子图案的第一光掩模。 生成对应于第二子图案的第二光掩模。

公开(公告)号：US09640402B1

公开(公告)日：2017-05-02

申请号：US15049351

申请日：2016-02-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Jiong Li

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/40

CPC classification number: H01L21/283 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/32139 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/513

Abstract: Methods for forming a gate structure of a circuit structure are provide. The methods for forming the gate structure may include: forming a first gate pattern in a gate mask layer, the forming including a first etching of rounded corner portions of the first gate pattern; forming a second gate pattern in the gate mask layer, the second gate pattern at least partially overlapping the first gate pattern, the forming including a second etching of rounded corner portions of the second gate pattern; and, etching the gate mask layer using the first gate pattern and second gate pattern to form the gate structure.

公开(公告)号：US09620380B1

公开(公告)日：2017-04-11

申请号：US14972804

申请日：2015-12-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xintuo Dai ,  Huang Liu ,  Jin Ping Liu ,  Jiong Li

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/033 ,  H01L27/108

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/10826 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for fabricating an integrated circuit includes providing an semiconductor wafer includes forming in an upper mandrel layer a first upper mandrel having a first critical dimension and a second upper mandrel having a second critical dimension; forming upper sidewall spacers along sidewalls of the first upper mandrel while leaving the second upper mandrel without sidewall spacers; removing the first upper mandrel from between the upper sidewall spacers; transferring a pattern of the upper sidewall spacers and of the second upper mandrel into a lower mandrel layer to form first lower mandrels according to the pattern of the upper sidewall spacers and a second lower mandrel according to the pattern of the second upper mandrel; and forming lower sidewall spacers along sidewalls of the first and second lower mandrels.

公开(公告)号：US09530689B2

公开(公告)日：2016-12-27

申请号：US14684949

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Deniz Elizabeth Civay ,  Jason Eugene Stephens ,  Jiong Li ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76811 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract translation: 提供了制造集成电路的方法。 一种方法包括分解用于半导体器件层的主图案布局，该半导体器件层包括目标金属线，目标金属线与目标互连通孔/触点成为第一子图案和第二子图案。 目标金属线被分解为作为第一子图案的一部分的第一线特征图案和作为第二子图案的一部分的第二线特征图案，使得第一和第二线特征图案具有限定 对应于目标互连通孔/触点的针脚。 生成对应于第一子图案的第一光掩模。 生成对应于第二子图案的第二光掩模。