公开(公告)号：US09947545B2

公开(公告)日：2018-04-17

申请号：US15437837

申请日：2017-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Jiong Li

IPC: H01L21/336 ,  H01L21/283 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/283 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/32139 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/513

Abstract: Methods for forming a gate structure of a circuit structure are provide. The methods for forming the gate structure may include: forming a first gate pattern in a gate mask layer, the forming including a first etching of rounded corner portions of the first gate pattern; forming a second gate pattern in the gate mask layer, the second gate pattern at least partially overlapping the first gate pattern, the forming including a second etching of rounded corner portions of the second gate pattern; and, etching the gate mask layer using the first gate pattern and second gate pattern to form the gate structure.

公开(公告)号：US20170345913A1

公开(公告)日：2017-11-30

申请号：US15165294

申请日：2016-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Haigou Huang ,  Xusheng Wu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first hard mask layer is formed above the dielectric layer. The first hard mask layer and the sacrificial material are the same material. A second hard mask layer is formed above the first hard mask layer. The second hard mask layer is patterned to define an opening therein exposing a portion of the first hard mask layer and being disposed above a portion of the placeholder gate structure. The exposed portion of the first hard mask layer and the portion of the sacrificial material of the placeholder gate structure disposed below the opening are removed to define a gate cut cavity and divide the placeholder gate structure into first and second segments. A dielectric material is formed in the gate cut cavity.

公开(公告)号：US10062772B2

公开(公告)日：2018-08-28

申请号：US15219370

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Xusheng Wu ,  Xintuo Dai

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L29/66795 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the isolation structure adjacent an interface between the fin and the isolation structure. The liner layer includes a material different than the isolation structure. A sacrificial gate structure is formed above a portion of the fin and includes a sacrificial gate insulation layer and a sacrificial gate structure. The sacrificial gate structure is removed. The sacrificial gate insulation layer is removed selectively to the liner layer. A replacement gate structure is formed above a portion of the fin in a cavity defined by removing the sacrificial gate structure.

公开(公告)号：US09991361B2

公开(公告)日：2018-06-05

申请号：US15165294

申请日：2016-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Haigou Huang ,  Xusheng Wu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first hard mask layer is formed above the dielectric layer. The first hard mask layer and the sacrificial material are the same material. A second hard mask layer is formed above the first hard mask layer. The second hard mask layer is patterned to define an opening therein exposing a portion of the first hard mask layer and being disposed above a portion of the placeholder gate structure. The exposed portion of the first hard mask layer and the portion of the sacrificial material of the placeholder gate structure disposed below the opening are removed to define a gate cut cavity and divide the placeholder gate structure into first and second segments. A dielectric material is formed in the gate cut cavity.

公开(公告)号：US09627274B1

公开(公告)日：2017-04-18

申请号：US15214670

申请日：2016-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haifeng Sheng ,  Xintuo Dai ,  Jinping Liu ,  Huang Liu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L21/823871 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/786

Abstract: One illustrative method disclosed herein includes, among other things, forming a first sacrificial layer comprising amorphous silicon or polysilicon material around a fin in a lateral space between a plurality of laterally spaced apart gate structures that are positioned around the fin, performing a first selective etching process to remove a first sacrificial layer selectively relative to surrounding material so as to expose the fin in the lateral space, forming an epi material on the exposed portion of the fin, and forming a second layer of a sacrificial material above the epi material. The method also includes selectively removing the second layer of sacrificial material relative to at least the first layer of material to thereby define a source/drain contact opening that exposes the epi material and forming a self-aligned trench conductive source/drain contact structure that is conductively coupled to the epi material.

公开(公告)号：US10833022B2

公开(公告)日：2020-11-10

申请号：US16654354

申请日：2019-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cung D. Tran ,  Huaxiang Li ,  Bradley Morgenfeld ,  Xintuo Dai ,  Sanggil Bae ,  Rui Chen ,  Md Motasim Bellah ,  Dongyue Yang ,  Minghao Tang ,  Christian J. Ayala ,  Ravi Prakash Srivastava ,  Kripa Nidhan Chauhan ,  Pavan Kumar Chinthamanipeta Sripadarao

IPC: G03F9/00 ,  G03F7/16 ,  G03F7/20 ,  H01L23/544 ,  H01L21/027 ,  H01L23/528 ,  H01L23/538

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

公开(公告)号：US20200152498A1

公开(公告)日：2020-05-14

申请号：US16188814

申请日：2018-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dongyue Yang ,  Keith H. Tabakman ,  Guanchen He ,  Xintuo Dai ,  Xueli Hao

IPC: H01L21/68 ,  H01L21/033 ,  H01L21/762 ,  H01L23/544

Abstract: Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer.

公开(公告)号：US20200051923A1

公开(公告)日：2020-02-13

申请号：US16654354

申请日：2019-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cung D. Tran ,  Huaxiang Li ,  Bradley Morgenfeld ,  Xintuo Dai ,  Sanggil Bae ,  Rui Chen ,  Md Motasim Bellah ,  Dongyue Yang ,  Minghao Tang ,  Christian J. Ayala ,  Ravi Prakash Srivastava ,  Kripa Nidhan Chauhan ,  Pavan Kumar Chinthamanipeta Sripadarao

IPC: H01L23/544 ,  G03F9/00 ,  H01L21/027 ,  G03F7/16

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

公开(公告)号：US20190219930A1

公开(公告)日：2019-07-18

申请号：US15869150

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dongyue Yang ,  Xintuo Dai ,  Dongsuk Park ,  Minghao Tang ,  Md Motasim Bellah ,  Pavan Kumar Chinthamanipeta Sripadarao ,  Cheuk Wun Wong

IPC: G03F7/20 ,  G03F9/00

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

公开(公告)号：US20170162430A1

公开(公告)日：2017-06-08

申请号：US14958224

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xintuo Dai ,  Huang Liu ,  Chang Ho Maeng

IPC: H01L21/764 ,  H01L23/31 ,  H01L23/528 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/3107 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/535

Abstract: Methods for producing integrated circuits and integrated circuits produced by such methods are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a base dielectric layer overlying a substrate. A sacrificial layer is formed overlying the base dielectric layer, and adjacent conductive components are formed in the sacrificial layer where the adjacent conductive components are physically separated by material of the sacrificial layer. The sacrificial layer is removed such that an air gap is defined between the adjacent conductive components, where the air gap overlies the base dielectric layer. A cap dielectric layer is formed overlying the base dielectric layer and the air gap to enclose the air gap within the integrated circuit.