公开(公告)号：US20170330934A1

公开(公告)日：2017-11-16

申请号：US15155761

申请日：2016-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John ZHANG ,  Lawrence CLEVENGER ,  Kangguo CHENG ,  Balasubramanian HARAN

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/786 ,  H01L21/306

CPC classification number: H01L29/0665 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.

公开(公告)号：US20190081155A1

公开(公告)日：2019-03-14

申请号：US15703221

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Kangguo CHENG ,  Nicolas LOUBET ,  Xin MIAO ,  Pietro MONTANINI ,  John ZHANG ,  Haigou HUANG ,  Jianwei PENG ,  Sipeng GU ,  Hui ZANG ,  Yi QI ,  Xusheng WU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.