公开(公告)号：US20200020769A1

公开(公告)日：2020-01-16

申请号：US16032878

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei PENG ,  Sang Woo LIM ,  Matthew Wahlquist STOKER ,  Huang LIU ,  Jinping LIU

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3x fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3x fin pitch, a TS formed on the RSD, and an ILD formed over the TS.

公开(公告)号：US20190206743A1

公开(公告)日：2019-07-04

申请号：US15860840

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Jianwei PENG ,  Yi QI ,  Hsien-Ching LO ,  Jerome CIAVATTI ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/823487 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2018 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.

公开(公告)号：US20170278925A1

公开(公告)日：2017-09-28

申请号：US15078247

申请日：2016-03-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei PENG ,  Xusheng WU

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L29/0649 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/3105 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of introducing SDB material with a lower etch rate during a formation of a t-shape SDB STI structure are provided. Embodiments include providing an STI region in a Si substrate; forming a hardmask over the STI region and the Si substrate; forming a cavity through the hardmask over the STI region, the cavity having a width greater than a width of the STI region; depositing a SDB material in the cavity with an etch rate lower than HDP oxide to form a t-shaped SDB STI structure; and removing the hardmask.

公开(公告)号：US20180374759A1

公开(公告)日：2018-12-27

申请号：US15630547

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. HOLT ,  Yi QI ,  Hsien-Ching LO ,  Jianwei PENG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure.

公开(公告)号：US20160190252A1

公开(公告)日：2016-06-30

申请号：US14679074

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie FENG ,  Yanxiang LIU ,  Shesh Mani PANDEY ,  Jianwei PENG ,  Francis BENISTANT

IPC: H01L29/08 ,  H01L21/265 ,  H01L29/24 ,  H01L21/3065 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract translation: 公开了一种形成具有突然垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第一掩模; 在栅电极的每一侧上在第二极性FET的鳍的相对侧上形成间隔物，第二极性与第一极性相反; 将第一掺杂剂注入到第二极性FET的鳍中; 在栅电极的每一侧蚀刻第二极性FET的鳍的空腔; 去除第一个面罩; 进行快速热退火（RTA）; 在每个空腔中外延生长第二极性FET的源极/漏极区域; 在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第二掩模; 以及在所述第二极性FET的源极/漏极区域中注入第二掺杂剂。

公开(公告)号：US20180204840A1

公开(公告)日：2018-07-19

申请号：US15407960

申请日：2017-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jianwei PENG ,  Xusheng WU

IPC: H01L27/092 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L27/0924 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/161 ,  H01L29/6681

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned junction structures and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for first type devices; and a plurality epitaxial grown fin structures for second type devices having sidewall liners.

公开(公告)号：US20160308005A1

公开(公告)日：2016-10-20

申请号：US15189079

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie FENG ,  Jianwei PENG ,  Yanxiang LIU ,  Shesh Mani PANDEY ,  Francis BENISTANT

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/78 ,  H01L21/265 ,  H01L21/268 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract translation: 公开了一种形成具有突然，垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在半导体鳍片上方并垂直于半导体鳍片形成栅电极; 在栅电极的相对侧上形成第一间隔物; 在所述翅片的相对侧上形成第二间隔物; 在第二间隔件之间形成邻近第一间隔件的翅片中的空腔; 在每个腔中部分地外延生长源/漏区; 将第一掺杂剂注入部分生长的源极/漏极区域中，其后可选择的RTA; 在空腔中外延生长源/漏区的剩余部分，原位掺杂有第二掺杂剂; 以及在源极/漏极区域中注入第三掺杂剂。

公开(公告)号：US20190081155A1

公开(公告)日：2019-03-14

申请号：US15703221

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Kangguo CHENG ,  Nicolas LOUBET ,  Xin MIAO ,  Pietro MONTANINI ,  John ZHANG ,  Haigou HUANG ,  Jianwei PENG ,  Sipeng GU ,  Hui ZANG ,  Yi QI ,  Xusheng WU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.

公开(公告)号：US20160293718A1

公开(公告)日：2016-10-06

申请号：US15180312

申请日：2016-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie FENG ,  Yanxiang LIU ,  Shesh Mani PANDEY ,  Jianwei PENG ,  Francis BENISTANT

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

公开(公告)号：US20160190251A1

公开(公告)日：2016-06-30

申请号：US14676912

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie FENG ,  Jianwei PENG ,  Yanxiang LIU ,  Shesh Mani PANDEY ,  Francis BENISTANT

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/24 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.