公开(公告)号：US20140131881A1

公开(公告)日：2014-05-15

申请号：US13673549

申请日：2012-11-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xin Wang ,  Changyong Xiao ,  Yue Hu ,  Yong Meng Lee ,  Meng Luo ,  Jialin Weng ,  Wei Hua Tong ,  Wen-Pin Peng

IPC: H01L23/48 ,  H01L21/20 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract translation: 本文提供集成电路和形成集成电路的方法。 在一个实施例中，形成集成电路的方法包括提供其中布置有嵌入式电触头的基底基板。 在基底基板上形成层间电介质，通过嵌入的电触头上的层间电介质蚀刻凹陷。 保护衬垫形成在凹部中并且在凹部中的嵌入式电触点的暴露表面上。 保护衬垫包括至少两个衬垫层，其在不同的蚀刻剂中具有实质上不同的蚀刻速率。 保护衬垫的一部分在嵌入的电触点的表面上被去除，以再次暴露凹陷中嵌入的电触点的表面。 在凹部中形成嵌入式电气互连。 嵌入式电互连覆盖在凹槽侧面上的保护衬垫。

公开(公告)号：US09123783B2

公开(公告)日：2015-09-01

申请号：US13673549

申请日：2012-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xin Wang ,  Changyong Xiao ,  Yue Hu ,  Yong Meng Lee ,  Meng Luo ,  Jialin Weng ,  Wei Hua Tong ,  Wen-Pin Peng

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract translation: 本文提供集成电路和形成集成电路的方法。 在一个实施例中，形成集成电路的方法包括提供其中布置有嵌入式电触头的基底基板。 在基底基板上形成层间电介质，通过嵌入的电触头上的层间电介质蚀刻凹陷。 保护衬垫形成在凹部中并且在凹部中的嵌入式电触点的暴露表面上。 保护衬垫包括至少两个衬垫层，其在不同的蚀刻剂中具有实质上不同的蚀刻速率。 保护衬垫的一部分在嵌入的电触点的表面上被去除，以再次暴露凹陷中嵌入的电触点的表面。 在凹部中形成嵌入式电气互连。 嵌入式电互连覆盖在凹槽侧面上的保护衬垫。

公开(公告)号：US09147572B2

公开(公告)日：2015-09-29

申请号：US13896022

申请日：2013-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish Kumar Jha ,  Haiting Wang ,  Meng Luo ,  Yong Meng Lee

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/02071 ,  H01L21/28238 ,  H01L21/31144 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.

Abstract translation: 公开了将替代金属栅极的长度控制到设计的栅极栅极长度的方法以及所得到的器件。 实施例可以包括从形成空腔的衬底上方去除虚拟栅极，其中腔的侧表面衬有氧化间隔层，并且空腔的底表面衬有栅极氧化物层，保形地形成牺牲氧化物层 衬底和空腔，并且从空腔的底表面和衬底去除牺牲氧化物层，留下衬在腔的侧表面的牺牲氧化物间隔物。