公开(公告)号：US09209258B2

公开(公告)日：2015-12-08

申请号：US14195330

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Feng Zhou ,  Tien-Ying Luo ,  Haiting Wang ,  Padmaja Nagaiah ,  Jean-Baptiste Laloe ,  Isabelle Pauline Ferain ,  Yong Meng Lee

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/40 ,  H01L29/51 ,  H01L21/311

CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/3247 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66545

Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.

Abstract translation: 提供了一种用于制造半导体器件的改进方法。 该方法包括：在基底上沉积电介质层; 在所述电介质层上沉积第一盖层; 在所述电介质层上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积虚拟盖层以形成部分栅极结构。 还提供了部分形成的半导体器件。 部分形成的半导体器件包括：衬底; 基底上的电介质层; 电介质层上的第一覆盖层; 介电层上的蚀刻停止层; 以及形成部分栅极结构的蚀刻停止层上的虚设盖层。

公开(公告)号：US09123783B2

公开(公告)日：2015-09-01

申请号：US13673549

申请日：2012-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xin Wang ,  Changyong Xiao ,  Yue Hu ,  Yong Meng Lee ,  Meng Luo ,  Jialin Weng ,  Wei Hua Tong ,  Wen-Pin Peng

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract translation: 本文提供集成电路和形成集成电路的方法。 在一个实施例中，形成集成电路的方法包括提供其中布置有嵌入式电触头的基底基板。 在基底基板上形成层间电介质，通过嵌入的电触头上的层间电介质蚀刻凹陷。 保护衬垫形成在凹部中并且在凹部中的嵌入式电触点的暴露表面上。 保护衬垫包括至少两个衬垫层，其在不同的蚀刻剂中具有实质上不同的蚀刻速率。 保护衬垫的一部分在嵌入的电触点的表面上被去除，以再次暴露凹陷中嵌入的电触点的表面。 在凹部中形成嵌入式电气互连。 嵌入式电互连覆盖在凹槽侧面上的保护衬垫。

公开(公告)号：US20140131881A1

公开(公告)日：2014-05-15

申请号：US13673549

申请日：2012-11-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xin Wang ,  Changyong Xiao ,  Yue Hu ,  Yong Meng Lee ,  Meng Luo ,  Jialin Weng ,  Wei Hua Tong ,  Wen-Pin Peng

IPC: H01L23/48 ,  H01L21/20 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract translation: 本文提供集成电路和形成集成电路的方法。 在一个实施例中，形成集成电路的方法包括提供其中布置有嵌入式电触头的基底基板。 在基底基板上形成层间电介质，通过嵌入的电触头上的层间电介质蚀刻凹陷。 保护衬垫形成在凹部中并且在凹部中的嵌入式电触点的暴露表面上。 保护衬垫包括至少两个衬垫层，其在不同的蚀刻剂中具有实质上不同的蚀刻速率。 保护衬垫的一部分在嵌入的电触点的表面上被去除，以再次暴露凹陷中嵌入的电触点的表面。 在凹部中形成嵌入式电气互连。 嵌入式电互连覆盖在凹槽侧面上的保护衬垫。

公开(公告)号：US09524911B1

公开(公告)日：2016-12-20

申请号：US14858412

申请日：2015-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hao-Cheng Tsai ,  Yong Meng Lee ,  Min-hwa Chi

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods for creating self-aligned FINFET SDBs for minimum gate junction pitch and epitaxy formation. Embodiments include forming separated openings in a hard mask on upper surfaces of Si fins; forming cavities in the fins, each of the cavities having a concave shape and a width extending under the hard mask on each side of the cavity; forming trenches in the fins, the trenches having an upper width substantially equal to a width of the openings and less than the width of a cavity; removing the hard mask; filling the trenches and the cavities with oxide, forming STI regions; forming an oxide mask layer on the upper surfaces of the fins and the STI regions; removing upper portions of the oxide in sections between the STI regions; and removing remaining portions of the oxide mask revealing the fins and upper surfaces of the STI regions.

Abstract translation: 用于创建自对准FINFET SDB的方法，用于最小栅极连接节距和外延形成。 实施例包括在Si散热片的上表面上形成硬掩模中的分开的开口; 在所述翅片中形成空腔，所述空腔中的每一个具有凹形形状和在所述空腔的每一侧上在所述硬掩模下方延伸的宽度; 在所述翅片中形成沟槽，所述沟槽的上宽度基本上等于所述开口的宽度并小于空腔的宽度; 去除硬面膜; 用氧化物填充沟槽和空腔，形成STI区域; 在鳍片和STI区域的上表面上形成氧化物掩模层; 去除STI区域之间部分氧化物的上部; 并且去除暴露出STI区域的翅片和上表面的氧化物掩模的剩余部分。

公开(公告)号：US09607989B2

公开(公告)日：2017-03-28

申请号：US14560049

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Yue Hu ,  Xin Wang ,  Yong Meng Lee ,  Wen-Pin Peng ,  Lun Zhao ,  Wei-Hua Tong

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.

公开(公告)号：US09202697B2

公开(公告)日：2015-12-01

申请号：US13946485

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tien-Ying Luo ,  Feng Zhou ,  Yan Ping Shen ,  Haiting Wang ,  Haoran Shi ,  Wei Hua Tong ,  Seung Kim ,  Yong Meng Lee

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/28176 ,  H01L29/6659

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract translation: 一种方法包括通过在衬底上生长界面层来形成栅极结构，在界面层上沉积高K层，在高K层上沉积TiN帽并在TiN帽上形成薄的阻挡层。 栅极结构退火。

公开(公告)号：US09147572B2

公开(公告)日：2015-09-29

申请号：US13896022

申请日：2013-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish Kumar Jha ,  Haiting Wang ,  Meng Luo ,  Yong Meng Lee

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/02071 ,  H01L21/28238 ,  H01L21/31144 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.

Abstract translation: 公开了将替代金属栅极的长度控制到设计的栅极栅极长度的方法以及所得到的器件。 实施例可以包括从形成空腔的衬底上方去除虚拟栅极，其中腔的侧表面衬有氧化间隔层，并且空腔的底表面衬有栅极氧化物层，保形地形成牺牲氧化物层 衬底和空腔，并且从空腔的底表面和衬底去除牺牲氧化物层，留下衬在腔的侧表面的牺牲氧化物间隔物。

公开(公告)号：US20140175562A1

公开(公告)日：2014-06-26

申请号：US13727218

申请日：2012-12-26

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Haiting Wang ,  Huang Liu ,  Yong Meng Lee ,  Songkram Srivathanakul

IPC: H01L21/28 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L21/76837 ,  H01L21/823468 ,  H01L21/823864

Abstract: A semiconductor structure in fabrication includes a NFET and a PFET. Spacers adjacent gate structures of the NFET and PFET have undesired divots that can lead to substrate damage from chemicals used in a subsequent etch. The fabrication also leaves hard masks over the gate structures with non-uniform height. The divots are filled with material resistant to the chemicals used in the etch. Excess filler is removed, and uniform height is restored. Further fabrication may then proceed.

Abstract translation: 制造中的半导体结构包括NFET和PFET。 NFET和PFET的相邻栅极结构的间隔具有不期望的凹陷，这可能导致在后续蚀刻中使用的化学品的基底损伤。 该制造也在具有不均匀高度的门结构上留下硬掩模。 这些图案填充有耐蚀刻中使用的化学品的材料。 去除多余的填料，恢复均匀的高度。 然后进一步制造。