公开(公告)号：US20180366579A1

公开(公告)日：2018-12-20

申请号：US15622591

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Ming-Cheng Chang ,  Thomas Merbeth

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L29/08 ,  H01L21/84

Abstract: A high voltage transistor may be formed on the basis of CMOS techniques for forming sophisticated SOI devices, wherein a fully depleted channel portion may result in low on-resistance and high breakdown voltage. Thus, an LDMOS-type transistor may be formed on the basis of a fully depleted drift region, thereby providing a high degree of scalability and process compatibility with sophisticated CMOS techniques.

公开(公告)号：US20170317161A1

公开(公告)日：2017-11-02

申请号：US15142332

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Ming-Cheng Chang ,  Ralf Richter

IPC: H01L49/02

CPC classification number: H01L28/84 ,  H01L21/76283 ,  H01L28/40 ,  H01L28/82

Abstract: The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

公开(公告)号：US20170250181A1

公开(公告)日：2017-08-31

申请号：US15054355

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L27/088 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475

Abstract: A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate electrodes formed over the surface of the semiconductor layer is provided. The semiconductor fins extend in parallel to each other along a first direction parallel to the surface of the semiconductor layer and have a first height in a second direction that is perpendicular to the first direction, and the gate electrodes comprise longitudinal portions extending parallel to the semiconductor fins along the first direction and, in particular, having a second height in the second direction lower than the first height.

公开(公告)号：US10593674B1

公开(公告)日：2020-03-17

申请号：US16129221

申请日：2018-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Nigel Chan ,  Elliot John Smith

IPC: H01L29/78 ,  H01L27/092 ,  H03K19/0948 ,  H01L21/762 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/088 ,  H01L27/02

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

公开(公告)号：US10134730B2

公开(公告)日：2018-11-20

申请号：US15642507

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/306 ,  H01L21/3213

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the semiconductor layer extending in parallel to each other along a first direction parallel to the surface of the semiconductor layer, and forming a plurality of gate electrodes comprising longitudinal portions extending parallel to the semiconductor fins along the first direction.

公开(公告)号：US20170309628A1

公开(公告)日：2017-10-26

申请号：US15642507

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Ran Yan ,  Bo Bai

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the semiconductor layer extending in parallel to each other along a first direction parallel to the surface of the semiconductor layer, and forming a plurality of gate electrodes comprising longitudinal portions extending parallel to the semiconductor fins along the first direction.

公开(公告)号：US20200083223A1

公开(公告)日：2020-03-12

申请号：US16129221

申请日：2018-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Nigel Chan ,  Elliot John Smith

IPC: H01L27/092 ,  H03K19/0948 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/762

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

公开(公告)号：US20190312038A1

公开(公告)日：2019-10-10

申请号：US15948016

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Elliot John Smith ,  Ming-Cheng Chang

IPC: H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092

Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which a contact element at the source side of a pull-down transistor in a RAM cell may connect to the back gate region in a fully depleted SOI transistor architecture. In this manner, the complexity of at least some metallization layers may be reduced, thereby providing the potential of reducing parasitic bit line capacitance. Furthermore, in some illustrative embodiments, the contact regime for connecting the back gate region to a reference potential may be omitted, thereby reducing overall floor space of respective designs.

公开(公告)号：US09941348B2

公开(公告)日：2018-04-10

申请号：US15142332

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Ming-Cheng Chang ,  Ralf Richter

IPC: H01L21/02 ,  H01L49/02 ,  H01L21/762

CPC classification number: H01L28/84 ,  H01L21/76283 ,  H01L28/40 ,  H01L28/82

Abstract: The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

公开(公告)号：US10559490B1

公开(公告)日：2020-02-11

申请号：US16107563

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Ming-Cheng Chang

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/306

Abstract: A device including multiple depth STI regions with sidewall profiles, and method of production thereof Embodiments include a top region having a substantially vertical sidewall profile; and a bottom region having a width greater than or equal to the top region and a sidewall profile.