公开(公告)号：US10658294B2

公开(公告)日：2020-05-19

申请号：US16411237

申请日：2019-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L23/50 ,  G06F30/392 ,  G06F30/394 ,  H01L27/118

Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.

公开(公告)号：US10366954B1

公开(公告)日：2019-07-30

申请号：US15962065

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain

IPC: H01L23/528 ,  H01L23/522 ,  G06F17/50 ,  H01L27/02 ,  H01L23/50

Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.

公开(公告)号：US20170125403A1

公开(公告)日：2017-05-04

申请号：US15286196

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain ,  Anurag Mittal ,  Sangmoon Kim

IPC: H01L27/06 ,  H01L29/66 ,  G06F17/50 ,  H01L27/11 ,  H01L27/02

CPC classification number: H01L27/0629 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1203 ,  H01L28/00 ,  H01L29/6609 ,  H01L29/8611

Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

公开(公告)号：US20170104005A1

公开(公告)日：2017-04-13

申请号：US15375890

申请日：2016-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Haufe ,  Ingolf Lorenz ,  Michael Zier ,  Ulrich Gerhard Hensel ,  Navneet Jain

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/0696 ,  H01L29/4916 ,  H01L29/78648

Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

公开(公告)号：US09634003B2

公开(公告)日：2017-04-25

申请号：US15063563

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

公开(公告)号：US09337099B1

公开(公告)日：2016-05-10

申请号：US14610260

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L21/44 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract translation: 提供了用于使具有不同大小的扩散区域的两个电池邻接的方法以及所得到的装置。 实施例包括：通过在两个单元之间的边界处形成虚拟栅极来邻接具有第一漏极和源极扩散区域的第一单元和具有大于第一扩散区域的第二漏极和源极扩散区域的第二单元; 形成连续的漏极扩散区域，其具有与伪栅极交叉的上部，并且包围整个第一漏极扩散区域和第二漏极扩散区域的一部分，并且具有从伪栅极开始的下部，并且包围第二漏极扩散区域的剩余部分 ; 形成作为连续漏极扩散区域的镜像的连续源极扩散区域; 以及在连续的漏极和源极扩散区之间在虚拟栅极之间形成多边形掩模，但是与连续的漏极和源极扩散区分离。

公开(公告)号：US10199378B2

公开(公告)日：2019-02-05

申请号：US15857202

申请日：2017-12-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8238

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

公开(公告)号：US10068918B2

公开(公告)日：2018-09-04

申请号：US15375890

申请日：2016-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Haufe ,  Ingolf Lorenz ,  Michael Zier ,  Ulrich Gerhard Hensel ,  Navneet Jain

IPC: H01L27/12 ,  H01L29/49 ,  H01L21/84 ,  H01L29/06

Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

公开(公告)号：US09893063B2

公开(公告)日：2018-02-13

申请号：US15420967

申请日：2017-01-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

公开(公告)号：US20170358565A1

公开(公告)日：2017-12-14

申请号：US15177417

申请日：2016-06-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ulrich Hensel ,  Michael Zier ,  Navneet Jain ,  Rainer Mann

IPC: H01L27/02 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/06 ,  H01L21/28 ,  H01L21/762 ,  H01L29/10 ,  H01L29/423 ,  H01L27/092 ,  H01L29/788

CPC classification number: H01L27/0207 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/11807 ,  H01L2027/11874

Abstract: The present disclosure provides an integrated circuit product including a plurality of standard cells, each standard cell of the plurality of standard cells being in abutment with at least one other standard cell of the plurality of standard cells, a continuous active region continuously extending across the plurality of standard cells, at least two active regions being separated by an intermediate diffusion break, wherein each standard cell comprises at least one PMOS device and at least one NMOS device, the at least one PMOS device being provided in and above the continuous active region and the at least one NMOS device being provided in and above the at least two active regions.