公开(公告)号：US10691862B2

公开(公告)日：2020-06-23

申请号：US15644288

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Neha Nayyar ,  Daniel J. Dechene ,  David C. Pritchard ,  George J. Kluth

IPC: G06F30/394 ,  H01L23/522 ,  H01L21/8234

Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.

公开(公告)号：US09941301B1

公开(公告)日：2018-04-10

申请号：US15388772

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Lixia Lei ,  Deniz E. Civay ,  Scott D. Luning ,  Neha Nayyar

IPC: H01L21/8234 ,  H01L27/12 ,  H01L29/49 ,  H01L21/84 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4916 ,  H01L29/7838

Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.

公开(公告)号：US20210057558A1

公开(公告)日：2021-02-25

申请号：US16548518

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/76 ,  H01L29/10 ,  H01L29/08

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

公开(公告)号：US10186524B2

公开(公告)日：2019-01-22

申请号：US15912141

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Lixia Lei ,  Deniz E. Civay ,  Scott D. Luning ,  Neha Nayyar

IPC: H01L27/12 ,  H01L29/49 ,  H01L21/84 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234

Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.