公开(公告)号：US09349641B2

公开(公告)日：2016-05-24

申请号：US14487250

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Oliver Aubel ,  Frank Feustel

IPC: H01L21/44 ,  H01L21/768 ,  H01L27/02 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

Abstract translation: 提供一种半导体晶片，其包括多个管芯，所述多个管芯中的每一个包括多个半导体器件，多个管芯密封件，所述多个管芯密封件中的每一个形成在所述多个管芯中的一个的周边， 以及多个导电连接件，所述多个导电连接中的每一个将所述多个模具密封件中的一个与所述多个模具密封件中的另一个连接。

公开(公告)号：US08653624B2

公开(公告)日：2014-02-18

申请号：US13952792

申请日：2013-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Hennesthal ,  Oliver Aubel ,  Jens Poppe ,  Holger Pagel ,  Andreas Kurz

IPC: H01L23/52

CPC classification number: H01L23/5256 ,  G11C17/16 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Metal fuses in semiconductor devices may be formed on the basis of additional mechanisms for obtaining superior electromigration in the fuse bodies. To this end, the compressive stress caused by the current-induced metal diffusion may be restricted or reduced in the fuse body, for instance, by providing a stress buffer region and/or by providing a dedicated metal agglomeration region. The concept may be applied to the metallization system and may also be used in the device level, when fabricating the metal fuse in combination with high-k metal gate electrode structures.

Abstract translation: 可以基于用于在保险丝体中获得优异的电迁移的附加机构来形成半导体器件中的金属熔丝。 为此，例如通过提供应力缓冲区域和/或通过提供专用的金属附聚区域，可以限制或减小由电流引起的金属扩散引起的压缩应力。 该概念可以应用于金属化系统，并且当与高k金属栅电极结构组合制造金属熔丝时也可以在器件级中使用。

公开(公告)号：US20160111382A1

公开(公告)日：2016-04-21

申请号：US14519291

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Oliver Aubel ,  Georg Talut ,  Thomas Werner

IPC: H01L23/60 ,  H01L23/532

CPC classification number: H01L23/53214 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2224/05006 ,  H01L2224/05546

Abstract: The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.

Abstract translation: 本公开涉及包括布置在多个垂直级上的多条连接线的半导体结构，所述多条连接线至少包括布置在第一垂直级中的第一连接线和布置在第二垂直方向上的第二连接线 与第一垂直水平不同的防水层，以及放置在将第一连接线与第二连接线分隔开的垂直空间的至少一部分中的击穿防止层。

公开(公告)号：US20160111381A1

公开(公告)日：2016-04-21

申请号：US14515986

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Frank Feustel ,  Oliver Aubel

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L23/564 ,  H01L21/02118 ,  H01L21/768 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L23/3171 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture.

Abstract translation: 半导体结构包括半导体衬底，设置在衬底上的一个或多个互连层和电路。 电路包括形成在基板上的多个电路元件和设置在一个或多个互连层中的多个电连接。 在一个或多个互连层中提供模具密封。 模密封泄漏检测材料布置在模具密封件和多个电连接件之间的一个或多个互连层中。 如果模具密封件是完整的，模具密封件可保护模具密封件泄漏检测材料免受潮湿。 模封密封泄漏检测材料适于在模具密封泄漏检测材料暴露于水分之后提供电路的可检测的修改。

公开(公告)号：US20160260794A1

公开(公告)日：2016-09-08

申请号：US14634978

申请日：2015-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Oliver Aubel ,  Frank Feustel ,  Thomas Werner

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L23/5227

Abstract: A method of forming a semiconductor device including an inductor is provided, including forming a first dielectric layer of a first dielectric material over a substrate, removing part of the first dielectric layer to create an opening in the first dielectric layer, filling the opening with a second dielectric layer of a second dielectric material different from the first dielectric material, forming a trench in the second dielectric layer, and filling the trench with a conductive material to form an inductor coil. A semiconductor device is provided that includes a first dielectric layer made of a first dielectric material, a second dielectric layer made of a second dielectric material different from the first dielectric material and embedded in the first dielectric layer and a trench filled with a conductive material and formed in the second dielectric layer, representing at least a part of an inductor coil of the inductor.

Abstract translation: 提供一种形成包括电感器的半导体器件的方法，包括在衬底上形成第一电介质材料的第一电介质层，去除第一电介质层的一部分以在第一电介质层中形成开口，用 第二电介质材料与第一介电材料不同的第二电介质层，在第二介电层中形成沟槽，并用导电材料填充沟槽以形成电感线圈。 提供一种半导体器件，其包括由第一电介质材料制成的第一电介质层，由与第一电介质材料不同并嵌入第一电介质层的第二电介质材料制成的第二电介质层和填充有导电材料的沟槽， 形成在第二电介质层中，代表电感器的电感线圈的至少一部分。

公开(公告)号：US20160240473A1

公开(公告)日：2016-08-18

申请号：US15137740

申请日：2016-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Oliver Aubel ,  Frank Feustel

IPC: H01L23/528 ,  H01L25/065 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

公开(公告)号：US09362239B2

公开(公告)日：2016-06-07

申请号：US14519291

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Oliver Aubel ,  Georg Talut ,  Thomas Werner

IPC: H01L23/52 ,  H01L23/60 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53214 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2224/05006 ,  H01L2224/05546

Abstract: The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.

Abstract translation: 本公开涉及包括布置在多个垂直级上的多条连接线的半导体结构，所述多条连接线至少包括布置在第一垂直级中的第一连接线和布置在第二垂直方向上的第二连接线 与第一垂直水平不同的防水层，以及放置在将第一连接线与第二连接线分隔开的垂直空间的至少一部分中的击穿防止层。

公开(公告)号：US09627317B2

公开(公告)日：2017-04-18

申请号：US15137740

申请日：2016-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Oliver Aubel ,  Frank Feustel

IPC: H01L23/528 ,  H01L21/56 ,  H01L23/58 ,  H01L23/532 ,  H01L25/065 ,  H01L21/288 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

公开(公告)号：US09455232B2

公开(公告)日：2016-09-27

申请号：US14515986

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Frank Feustel ,  Oliver Aubel

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/02 ,  H01L21/66 ,  H01L23/58 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/564 ,  H01L21/02118 ,  H01L21/768 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L23/3171 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture.

Abstract translation: 半导体结构包括半导体衬底，设置在衬底上的一个或多个互连层和电路。 电路包括形成在基板上的多个电路元件和设置在一个或多个互连层中的多个电连接。 在一个或多个互连层中提供模具密封。 模密封泄漏检测材料布置在模具密封件和多个电连接件之间的一个或多个互连层中。 如果模具密封件是完整的，模具密封件可保护模具密封件泄漏检测材料免受潮湿。 模封密封泄漏检测材料适于在模具密封泄漏检测材料暴露于水分之后提供电路的可检测的修改。

公开(公告)号：US20160079116A1

公开(公告)日：2016-03-17

申请号：US14487250

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Oliver Aubel ,  Frank Feustel

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/56 ,  H01L27/02

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

Abstract translation: 提供一种半导体晶片，其包括多个管芯，所述多个管芯中的每一个包括多个半导体器件，多个管芯密封件，所述多个管芯密封件中的每一个形成在所述多个管芯中的一个的周边， 以及多个导电连接件，所述多个导电连接中的每一个将所述多个模具密封件中的一个与所述多个模具密封件中的另一个连接。