公开(公告)号：US10649026B2

公开(公告)日：2020-05-12

申请号：US15474104

申请日：2017-03-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Oliver D. Patterson ,  Peter Lin ,  Weihong Gao

IPC: G01R31/28 ,  G01R31/307 ,  H01L21/66

Abstract: A method in which connectivity tests of integrated circuit structures in a die are performed. The connectivity tests are performed at a first level of the die. Potential defect locations are identified in the die indicating via locations susceptible to systematic failure due to via opens or via shorts. The potential defect locations are translated to via locations for a second level of the die. The second level is below the first level. After translating the hot spot, the second level is inspected for defects. The via locations on the first level are inspected for defects. All defects for the second level are translated to the via locations for the first level. A net trace of defects is created using prior level subtraction of the translated defects for the second level and the defects for the first level.

公开(公告)号：US09390884B2

公开(公告)日：2016-07-12

申请号：US14274042

申请日：2014-05-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric C. Harley ,  Oliver D. Patterson ,  Kevin T. Wu

IPC: H01L21/00 ,  H01J37/22 ,  H01J37/244 ,  G01N23/225 ,  G01B15/02

CPC classification number: H01J37/222 ,  G01B15/02 ,  G01N23/2251 ,  H01J37/244 ,  H01J2237/063 ,  H01J2237/221 ,  H01J2237/24495 ,  H01J2237/24592

Abstract: A semiconductor substrate inspection system includes an e-beam inspection system configured to deliver electrons to a specimen semiconductor substrate. A sensor is configured to detect reflected electrons that reflect off the surface of the specimen semiconductor substrate. An analysis unit is configured to determine a number of electrons received by the semiconductor substrate, and to determine at least one target region including at least one defect of the semiconductor substrate. A reference image module is in electrical communication with the analysis unit. The reference image module is configured to generate a first digital image having a plurality of pixels, and to adjust a gray-scale level of the pixels included in the target region based on the number electrons included in each pixel to generate a second digital image that excludes the at least one defect.

Abstract translation: 半导体衬底检查系统包括被配置为将电子传递到样本半导体衬底的电子束检查系统。 传感器被配置为检测从样本半导体衬底的表面反射的反射电子。 分析单元被配置为确定由半导体衬底接收的电子数量，并且确定至少一个包括半导体衬底的至少一个缺陷的目标区域。 参考图像模块与分析单元电连通。 参考图像模块被配置为生成具有多个像素的第一数字图像，并且基于包括在每个像素中的数量的电子像素来调整包括在目标区域中的像素的灰度级别以产生第二数字图像， 排除至少一个缺陷。

公开(公告)号：US20190113469A1

公开(公告)日：2019-04-18

申请号：US15786986

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Oliver D. Patterson ,  Richard F. Hafer ,  Dave M. Salvador ,  Yue Ke

IPC: G01N23/22 ,  H01J37/21 ,  G01N23/225 ,  H01J37/20

Abstract: A method of inspecting semiconductors and a semiconductor inspection system are disclosed. In an embodiment, the method comprises directing a charged particle beam onto a semiconductor device at an angle in a range between five degrees and eighty-five degrees from a normal to a top surface of the semiconductor; scanning the particle beam across a field of the semiconductor device; adjusting the semiconductor to maintain the particle beam at a defined focus on the semiconductor while scanning the particle beam across the field of the semiconductor device; detecting secondary and backscattered electrons from the semiconductor; and processing the detected secondary and backscattered electrons to inspect for defined conditions of the semiconductor. In an embodiment, the particle beam is maintained at the defined focus on the semiconductor device by controlling the position of the semiconductor device relative to a beam emitter that emits the particle beam.

公开(公告)号：US20170154687A1

公开(公告)日：2017-06-01

申请号：US14954151

申请日：2015-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhigang Song ,  Oliver D. Patterson ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

IPC: G11C29/04 ,  H01L21/768 ,  H01L23/58 ,  H01L21/66 ,  H01L27/11 ,  H01L27/108

CPC classification number: G11C29/04 ,  G11C29/025 ,  G11C29/56008 ,  G11C2029/0403 ,  G11C2029/5602 ,  H01L22/12 ,  H01L22/14 ,  H01L22/30 ,  H01L23/585 ,  H01L27/1104

Abstract: A SRAM-like electron beam inspection (EBI) structure and method for determining defects in integrated circuits inline during the production process at a level that enables earlier detection during fabrication. Initial layers, such as active layer, poly gate and contact of an IC are first fabricated, and a conductive mesh with horizontal components is provided above the contact layers connecting contact nodes of the contact layers. Voltage contrast is observed during EBI to detect short-circuits, open-circuits, or leakage currents formed between the horizontal components of the conductive mesh and metallized islands placed therebetween.

公开(公告)号：US09293382B2

公开(公告)日：2016-03-22

申请号：US14522626

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Norbert Arnold ,  Jin Liu ,  Brian W. Messenger ,  Oliver D. Patterson

IPC: H01L23/58 ,  H01L27/12 ,  G01R31/26 ,  H01L21/20 ,  H01L21/66 ,  H01L49/02 ,  H01L21/84 ,  H01L29/66 ,  H01L27/108 ,  H01L21/762

CPC classification number: H01L22/14 ,  H01L21/762 ,  H01L21/84 ,  H01L22/32 ,  H01L22/34 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/60 ,  H01L29/66181

Abstract: A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.