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    TUNABLE POLY RESISTORS FOR HYBRID REPLACEMENT GATE TECHNOLOGY AND METHODS OF MANUFACTURING
    4.
    发明申请
    TUNABLE POLY RESISTORS FOR HYBRID REPLACEMENT GATE TECHNOLOGY AND METHODS OF MANUFACTURING 审中-公开
    混合替代浇口技术及其制造方法的可调聚合电阻

    公开(公告)号：US20150228708A1

    公开(公告)日：2015-08-13

    申请号：US14176746

    申请日：2014-02-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Andrei SIDELNICOV ,  Peter BAARS

    IPC: H01L49/02 ,  H01L21/02 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/06 ,  H01L21/321

    CPC classification number: H01L28/20 ,  H01L21/02186 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/32115 ,  H01L21/32139 ,  H01L27/0629 ,  H01L27/0802 ,  H01L29/0649 ,  H01L29/66545

    Abstract: A poly resistor manufacturing method which allows resistor targeting and/or tuning by process rather than by design is disclosed. Embodiments include forming a high-k dielectric on a STI layer; forming a Ti layer on the high-k dielectric; forming a dummy Si layer on the TiN layer; forming spacers at opposite sides of the high-k dielectric, TiN, and dummy Si layers; forming an ILD surrounding the spacers; removing a portion of the dummy Si layer adjacent to each spacer, down to the TiN layer, to form a metal resistor end region; filling each metal resistor end region with a pWF stack; recessing the dummy Si layer between the pWF stacks; forming a TiN hardmask over the ILD, the spacers, the pWF stacks, and the recessed dummy Si layer; forming a nWF stack over the TiN hardmask; and planarizing the nWF metal stack and the TiN hardmask down to the ILD.

    Abstract translation: 公开了一种通过工艺而不是通过设计来实现电阻器靶向和/或调谐的多电阻器制造方法。 实施方式包括在STI层上形成高k电介质; 在高k电介质上形成Ti层; 在TiN层上形成虚拟Si层; 在高k电介质，TiN和虚拟Si层的相对侧形成间隔物; 形成围绕所述间隔物的ILD; 去除与每个间隔物相邻的虚拟Si层的一部分，直到TiN层，以形成金属电阻器端区; 用pWF堆叠填充每个金属电阻器端部区域; 在pWF堆叠之间凹陷虚拟Si层; 在ILD上形成TiN硬掩模，间隔物，pWF堆叠和凹陷的虚设Si层; 在TiN硬掩模上形成nWF堆叠; 并将nWF金属堆叠和TiN硬掩模平面化到ILD。

    MOL INSITU PT REWORK SEQUENCE
    5.
    发明申请
    MOL INSITU PT REWORK SEQUENCE 审中-公开
    MOL INSITU PT REWORK序列

    公开(公告)号：US20150028431A1

    公开(公告)日：2015-01-29

    申请号：US14513759

    申请日：2014-10-14

    Applicant: Globalfoundries Inc.

    Inventor： Peter BAARS ,  Marco LEPPER ,  Uwe KAHLER ,  Vivien SCHROEDER

    IPC: H01L21/285 ,  H01L29/49

    CPC classification number: H01L21/2855 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/32134 ,  H01L29/4958 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

    Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.

    Abstract translation: 在形成含Pt的NiSi之后剩余的Pt残余物的量通过在形成浇口间隔件的同时进行O2闪光，然后清洗并应用Aqua Regia的第二次应用来减少。 实施例包括在半导体衬底上溅射沉积Ni / Pt层，退火Ni / Pt层，湿剥离未反应的Ni，退火Ni剥离的Ni / Pt层，从退火的Ni / Pt层剥离未反应的Pt，例如， Aqua Regia，用氧等离子体处理Pt剥离的Ni / Pt层，清洁Ni / Pt层，以及从清洁的Ni / Pt层剥离未反应的Pt，例如，通过第二次应用Aqua Regia。

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