公开(公告)号：US20160126239A1

公开(公告)日：2016-05-05

申请号：US14928272

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jagar Singh ,  Sanford Chu

IPC: H01L27/06 ,  H01L23/552 ,  H01L49/02

CPC classification number: H01L27/0682 ,  H01L23/552 ,  H01L28/20 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.

Abstract translation: 提供了具有由MIM电容器材料形成的电阻结构的集成电路和用于制造这种集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供具有电阻器区域和电容器区域的半导体衬底。 该方法包括在电阻器区域和半导体衬底的电容器区域上沉积电容器材料。 该方法还包括从电阻器区域中的电容器材料形成电阻器结构。 此外，该方法包括在电阻器区域中形成到电阻器结构的电连接。

公开(公告)号：US10115719B2

公开(公告)日：2018-10-30

申请号：US14928272

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jagar Singh ,  Sanford Chu

IPC: H01L23/552 ,  H01L27/06 ,  H01L49/02

Abstract: Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.

公开(公告)号：US09530833B2

公开(公告)日：2016-12-27

申请号：US14307078

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dina H. Triyoso ,  Sanford Chu ,  Johannes Mueller ,  Patrick Polakowski

IPC: H01L29/92 ,  H01L27/108 ,  H01L49/02 ,  H01L27/115 ,  H01L27/08

CPC classification number: H01L28/55 ,  H01L27/0805 ,  H01L27/1085 ,  H01L27/11502 ,  H01L28/40

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Abstract translation: 本文公开的说明性方法包括提供半导体结构。 半导体结构包括设置在半导体衬底上的第一层间电介质。 第一电容器的第一电极形成在第一层间电介质上。 第一电介质材料层沉积在第一电容器和第一层间电介质的第一电极上。 一层导电材料沉积在第一介电材料层上。 第一电容器的第二电极和第二电容器的第一电极由导电材料层形成。 在形成第一电容器的第二电极和第二电容器的第一电极之后，沉积第二电介质材料层，并且第二电容器的第二电极形成在第二电介质材料层上。

公开(公告)号：US20160064472A1

公开(公告)日：2016-03-03

申请号：US14835278

申请日：2015-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lili Cheng ,  Dina H. Triyoso ,  Jeasung Park ,  David Paul Brunco ,  Robert Fox ,  Sanford Chu

IPC: H01L49/02 ,  G06F17/50 ,  H01L21/02 ,  H01L23/522 ,  H01L21/822

CPC classification number: H01L28/60 ,  G06F17/5068 ,  H01L21/02181 ,  H01L21/02189 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract translation: 提供了包括MIMCAP器件的集成电路和形成集成电路的方法。 形成包括MIMCAP器件的集成电路的示例性方法包括预先确定MIMCAP器件的底部高K层或顶部高K层中的至少之一的厚度，然后制造MIMCAP器件。 预先确定的厚度是基于MIMCAP器件的预定的TDDB寿命和MIMCAP器件所采用的施加电压偏置下的最小目标电容密度而建立的。 MIMCAP器件包括设置在底部电极上的底部电极和电介质层。 电介质层包括层叠的各层，包括底部高K层，顶部高K层和夹在其间的下部K层。 底部高K层或顶部高K层中的至少一层具有预定厚度。

公开(公告)号：US09583557B2

公开(公告)日：2017-02-28

申请号：US14835278

申请日：2015-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lili Cheng ,  Dina H. Triyoso ,  Jeasung Park ,  David Paul Brunco ,  Robert Fox ,  Sanford Chu

IPC: H01L21/00 ,  H01L49/02 ,  H01L23/522 ,  H01L21/02 ,  G06F17/50

CPC classification number: H01L28/60 ,  G06F17/5068 ,  H01L21/02181 ,  H01L21/02189 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract translation: 提供了包括MIMCAP器件的集成电路和形成集成电路的方法。 形成包括MIMCAP器件的集成电路的示例性方法包括预先确定MIMCAP器件的底部高K层或顶部高K层中的至少之一的厚度，然后制造MIMCAP器件。 预先确定的厚度是基于MIMCAP器件的预定的TDDB寿命和MIMCAP器件所采用的施加电压偏置下的最小目标电容密度而建立的。 MIMCAP器件包括设置在底部电极上的底部电极和电介质层。 电介质层包括层叠的各层，包括底部高K层，顶部高K层和夹在其间的下部K层。 底部高K层或顶部高K层中的至少一层具有预定厚度。

公开(公告)号：US20150364535A1

公开(公告)日：2015-12-17

申请号：US14307078

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dina H. Triyoso ,  Sanford Chu ,  Johannes Mueller ,  Patrick Polakowski

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/55 ,  H01L27/0805 ,  H01L27/1085 ,  H01L27/11502 ,  H01L28/40

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Abstract translation: 本文公开的说明性方法包括提供半导体结构。 半导体结构包括设置在半导体衬底上的第一层间电介质。 第一电容器的第一电极形成在第一层间电介质上。 第一电介质材料层沉积在第一电容器和第一层间电介质的第一电极上。 一层导电材料沉积在第一介电材料层上。 第一电容器的第二电极和第二电容器的第一电极由导电材料层形成。 在形成第一电容器的第二电极和第二电容器的第一电极之后，沉积第二电介质材料层，并且第二电容器的第二电极形成在第二电介质材料层上。