公开(公告)号：US09865608B2

公开(公告)日：2018-01-09

申请号：US15162151

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc. ,  Fraunhofer Gesellschaft zur Foerderung der angewandten Forschung e.V. ,  NaMLab gGmbH

Inventor： Johannes Mueller ,  Stefan Mueller ,  Stefan Flachowsky

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L27/11507

CPC classification number: H01L27/11507 ,  H01L21/28291 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/78391

Abstract: A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.

公开(公告)号：US09530833B2

公开(公告)日：2016-12-27

申请号：US14307078

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dina H. Triyoso ,  Sanford Chu ,  Johannes Mueller ,  Patrick Polakowski

IPC: H01L29/92 ,  H01L27/108 ,  H01L49/02 ,  H01L27/115 ,  H01L27/08

CPC classification number: H01L28/55 ,  H01L27/0805 ,  H01L27/1085 ,  H01L27/11502 ,  H01L28/40

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Abstract translation: 本文公开的说明性方法包括提供半导体结构。 半导体结构包括设置在半导体衬底上的第一层间电介质。 第一电容器的第一电极形成在第一层间电介质上。 第一电介质材料层沉积在第一电容器和第一层间电介质的第一电极上。 一层导电材料沉积在第一介电材料层上。 第一电容器的第二电极和第二电容器的第一电极由导电材料层形成。 在形成第一电容器的第二电极和第二电容器的第一电极之后，沉积第二电介质材料层，并且第二电容器的第二电极形成在第二电介质材料层上。

公开(公告)号：US20160268271A1

公开(公告)日：2016-09-15

申请号：US15162151

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc. ,  Fraunhofer Gesellschaft zur Foerderung der angewandten Forschung e.V. ,  NaMLab gGmbH

Inventor： Johannes Mueller ,  Stefan Mueller ,  Stefan Flachowsky

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L27/11507 ,  H01L21/28291 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/78391

Abstract: A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.

Abstract translation: 本文公开的方法包括提供半导体结构，所述半导体结构包括半导体衬底和栅极堆叠，所述栅极堆叠在衬底上包括栅极绝缘材料，栅极绝缘材料上方的浮置栅电极材料，铁电晶体管绝缘体 所述浮栅电极材料和所述铁电晶体管电介质上的顶电极材料，执行第一图案化工艺以去除所述顶电极材料和所述铁电晶体管电介质的部分，并且在所述第一图案化工艺之后执行第二图案化工艺以去除所述 浮栅电极材料和栅极绝缘材料，其中栅极结构的上部的投影面积垂直于衬底的厚度方向的平面上的尺寸小于栅极结构的下部的投影面积， 飞机。

公开(公告)号：US09269785B2

公开(公告)日：2016-02-23

申请号：US14165209

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes Mueller ,  Dina H. Triyoso ,  Robert Binder ,  Joachim Metzger ,  Patrick Polakowski

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/51 ,  H01L21/02 ,  H01L21/3105 ,  H01L27/115

CPC classification number: H01L29/516 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/28291 ,  H01L21/3105 ,  H01L27/11507 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6684 ,  H01L29/78391

Abstract: The present disclosure provides a semiconductor device comprising a substrate, an undoped HfO2 layer formed over the substrate and a TiN layer formed on the HfO2 layer. Herein, the undoped HfO2 layer is at least partially ferroelectric. In illustrative methods for forming a semiconductor device, an undoped amorphous HfO2 layer is formed over a semiconductor substrate and a TiN layer is formed on the undoped amorphous HfO2 layer. A thermal annealing process is performed for at least partially inducing a ferroelectric phase in the undoped amorphous HfO2 layer.

Abstract translation: 本公开提供了一种半导体器件，其包括衬底，在衬底上形成的未掺杂的HfO 2层和形成在HfO 2层上的TiN层。 这里，未掺杂的HfO 2层至少部分为铁电体。 在用于形成半导体器件的说明性方法中，在半导体衬底上形成未掺杂的非晶HfO 2层，并且在未掺杂的非晶HfO 2层上形成TiN层。 进行热退火处理以至少部分地诱导未掺杂的无定形HfO 2层中的铁电相。

公开(公告)号：US09318315B2

公开(公告)日：2016-04-19

申请号：US14176208

申请日：2014-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes Mueller ,  Dina H. Triyoso ,  Mark Gerard Nolan ,  Wenke Weinreich ,  Konrad Seidel ,  Patrick Polakowski

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L21/02107 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/66181 ,  H01L29/94

Abstract: The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Abstract translation: 本发明提供集成电路元件和具有高容量的集成电路元件和MIM / MIS电容器，以及集成电路元件和集成MIM / MIS电容器的形成方法以及控制集成电路元件和集成MIM / MIS电容器的方法。 在各个方面，提供基板，并且在基板上形成电介质层或绝缘层。 此外，在电介质层或绝缘层上设置电极层。 这里，电介质层或绝缘层处于反铁电相。 在各种示例性实施例中，集成电路元件可以实现MOSFET结构或电容器结构。

公开(公告)号：US20150014813A1

公开(公告)日：2015-01-15

申请号：US14176208

申请日：2014-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes Mueller ,  Dina H. Triyoso ,  Mark Gerard Nolan ,  Wenke Weinreich ,  Konrad Seidel ,  Patrick Polakowski

IPC: H01L49/02 ,  H01L21/02

CPC classification number: H01L21/02107 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/66181 ,  H01L29/94

Abstract: The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Abstract translation: 本发明提供集成电路元件和具有高容量的集成电路元件和MIM / MIS电容器，以及集成电路元件和集成MIM / MIS电容器的形成方法以及控制集成电路元件和集成MIM / MIS电容器的方法。 在各个方面，提供基板，并且在基板上形成电介质层或绝缘层。 此外，在电介质层或绝缘层上设置电极层。 这里，电介质层或绝缘层处于反铁电相。 在各种示例性实施例中，集成电路元件可以实现MOSFET结构或电容器结构。

公开(公告)号：US20150214322A1

公开(公告)日：2015-07-30

申请号：US14165209

申请日：2014-01-27

Applicant: Globalfoundries Inc.

Inventor： Johannes Mueller ,  Dina H. Triyoso ,  Robert Binder ,  Joachim Metzger ,  Patrick Polakowski

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/3105 ,  H01L27/115

CPC classification number: H01L29/516 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/28291 ,  H01L21/3105 ,  H01L27/11507 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6684 ,  H01L29/78391

Abstract: The present disclosure provides a semiconductor device comprising a substrate, an undoped HfO2 layer formed over the substrate and a TiN layer formed on the HfO2 layer. Herein, the undoped HfO2 layer is at least partially ferroelectric. In illustrative methods for forming a semiconductor device, an undoped amorphous HfO2 layer is formed over a semiconductor substrate and a TiN layer is formed on the undoped amorphous HfO2 layer. A thermal annealing process is performed for at least partially inducing a ferroelectric phase in the undoped amorphous HfO2 layer.

Abstract translation: 本公开提供了一种半导体器件，其包括衬底，在衬底上形成的未掺杂的HfO 2层和形成在HfO 2层上的TiN层。 这里，未掺杂的HfO 2层至少部分是铁电的。 在用于形成半导体器件的说明性方法中，在半导体衬底上形成未掺杂的非晶HfO 2层，并且在未掺杂的非晶HfO 2层上形成TiN层。 进行热退火处理以至少部分地诱导未掺杂的无定形HfO 2层中的铁电相。

公开(公告)号：US20160064510A1

公开(公告)日：2016-03-03

申请号：US14468839

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc. ,  Fraunhofer Gesellschaft zur Foerderung der angewandten Forschung e.V. ,  NaMLab gGmbH

Inventor： Johannes Mueller ,  Stefan Mueller ,  Stefan Flachowsky

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L27/11507 ,  H01L29/40111 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/78391

Abstract: An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.

Abstract translation: 本文公开的说明性器件包括半导体衬底。 衬底包括源极区，漏极区和沟道区。 沟道区域布置在源极区域和漏极区域之间。 栅极绝缘层设置在沟道区域的上方。 在栅绝缘层上设置浮栅电极。 在浮栅电极上设置铁电材料层。 顶层电极设置在铁电材料层上。 顶部电极在与半导体衬底的厚度方向垂直的平面上的投影面积小于浮动栅电极在平面上的投影面积。

公开(公告)号：US20150364535A1

公开(公告)日：2015-12-17

申请号：US14307078

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dina H. Triyoso ,  Sanford Chu ,  Johannes Mueller ,  Patrick Polakowski

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/55 ,  H01L27/0805 ,  H01L27/1085 ,  H01L27/11502 ,  H01L28/40

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Abstract translation: 本文公开的说明性方法包括提供半导体结构。 半导体结构包括设置在半导体衬底上的第一层间电介质。 第一电容器的第一电极形成在第一层间电介质上。 第一电介质材料层沉积在第一电容器和第一层间电介质的第一电极上。 一层导电材料沉积在第一介电材料层上。 第一电容器的第二电极和第二电容器的第一电极由导电材料层形成。 在形成第一电容器的第二电极和第二电容器的第一电极之后，沉积第二电介质材料层，并且第二电容器的第二电极形成在第二电介质材料层上。