公开(公告)号：US11288430B2

公开(公告)日：2022-03-29

申请号：US15822661

申请日：2017-11-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anupam Dutta ,  Tamilmani Ethirajan

IPC: G06F30/367 ,  G06F30/30

Abstract: A simulation circuit, that simulates characteristics of transistors is produced to include: an isolation body resistor representing resistance of a channel isolation portion of a transistor; a main body resistor representing resistance of main channel portion of the transistor; an isolation transistor connected to the isolation body resistor; and a body-contact transistor connected to the main body resistor. Simulated data is generated by supplying test inputs to the simulation circuit, while selectively activating either the isolation transistor or the body-contact transistor. Test data is generated by supplying the test inputs to the transistors, and measuring output of the transistors. The simulated data is compared to the test data to identify data differences. The design of the transistors is changed to reduce the data differences. The generation of test data, comparing, and design changes are repeated, until the data differences are within a threshold.

公开(公告)号：US20210273061A1

公开(公告)日：2021-09-02

申请号：US16803711

申请日：2020-02-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Tamilmani Ethirajan ,  Zhenyu Hu ,  Tung-Hsing Lee

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/73

Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

公开(公告)号：US11721621B2

公开(公告)日：2023-08-08

申请号：US17527606

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shweta Vasant Khokale ,  Kaustubh Shanbhag ,  Tamilmani Ethirajan

IPC: H01L23/522 ,  H01L27/12 ,  H01L21/84 ,  H01L23/528

CPC classification number: H01L23/5225 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/1203

Abstract: Structures including stacked field-effect transistors and methods of forming a structure including stacked field-effect transistors. The structure includes a field-effect transistor having a first active gate, a second active gate, and a drain region that is positioned in a horizontal direction between the first and second active gates. The structure further includes a back-end-of-line stack having a first metal level and a second metal level over the field-effect transistor. The first metal level includes a first interconnect, a second interconnect, and a third interconnect, and the second metal level includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is positioned in a vertical direction between the fourth interconnect and the drain region, and the third interconnect is positioned in the horizontal direction between the first and second interconnects.

公开(公告)号：US20230154844A1

公开(公告)日：2023-05-18

申请号：US17527606

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shweta Vasant Khokale ,  Kaustubh Shanbhag ,  Tamilmani Ethirajan

IPC: H01L23/522 ,  H01L27/12 ,  H01L23/528 ,  H01L21/84

CPC classification number: H01L23/5225 ,  H01L27/1203 ,  H01L23/5226 ,  H01L23/5286 ,  H01L21/84

Abstract: Structures including stacked field-effect transistors and methods of forming a structure including stacked field-effect transistors. The structure includes a field-effect transistor having a first active gate, a second active gate, and a drain region that is positioned in a horizontal direction between the first and second active gates. The structure further includes a back-end-of-line stack having a first metal level and a second metal level over the field-effect transistor. The first metal level includes a first interconnect, a second interconnect, and a third interconnect, and the second metal level includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is positioned in a vertical direction between the fourth interconnect and the drain region, and the third interconnect is positioned in the horizontal direction between the first and second interconnects.

公开(公告)号：US11264470B2

公开(公告)日：2022-03-01

申请号：US16803711

申请日：2020-02-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Tamilmani Ethirajan ,  Zhenyu Hu ,  Tung-Hsing Lee

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/73 ,  H01L29/10 ,  H01L29/423

Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

公开(公告)号：US11158624B1

公开(公告)日：2021-10-26

申请号：US16857298

申请日：2020-04-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Wenjun Li ,  Chen Perkins Yan ,  Tamilmani Ethirajan ,  Cole E. Zemke

IPC: H01L27/08 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8234 ,  H03F3/195 ,  H01L27/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to unitary Cascode cells with resistance and capacitance optimization, and methods of manufacture. The structure includes a common source FET (CS-FET) in a first portion of a single common semiconductor region, the CS-FET comprising a source region and a drain region, a common gate FET (CG-FET) in a second portion of the single common semiconductor region, the CG-FET comprising a source region and a drain region, and a doped connecting region of the single common semiconductor region, connecting the drain of the CS-FET and the source of the CG-FET.