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公开(公告)号:US11855074B2
公开(公告)日:2023-12-26
申请号:US17170325
申请日:2021-02-08
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Zhiqing Li , William J. Taylor, Jr. , Anindya Nath
IPC: H01L27/02
CPC classification number: H01L27/0262
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge devices and methods of manufacture. The structure includes: a plurality of regions of a first dopant type; insulator material separating each region of the plurality of regions of the first dopant type; and a substrate contacting the plurality of regions of the first dopant type, the substrate comprising a base region of a second dopant type different than the first dopant type and an outer segment surrounding the plurality of regions of the first dopant type, the outer segment comprises an electrical resistivity higher than the second dopant type.
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公开(公告)号:US11435982B2
公开(公告)日:2022-09-06
申请号:US16776909
申请日:2020-01-30
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Hemant M. Dixit , Julien Frougier , Bipul C. Paul , William J. Taylor, Jr.
Abstract: Embodiments of the disclosure provide a system for providing a true random number (TRN) or physically unclonable function (PUF), including: an array of voltage controlled magnetic anisotropy (VCMA) cells; a voltage pulse tuning circuit for generating and applying a stochastically tuned voltage pulse to the VCMA cells in the array of VCMA cells, wherein the stochastically tuned voltage pulse has a magnitude and duration that provides a 50%-50% switching distribution of the VCMA cells in the array of VCMA cells; and a bit output system for reading a state of each of the VCMA cells in the array of VCMA cells to provide a TRN or PUF.
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公开(公告)号:US11543604B2
公开(公告)日:2023-01-03
申请号:US17223059
申请日:2021-04-06
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: William J. Taylor, Jr.
IPC: G02B6/42
Abstract: Disclosed is a chip structure that includes heater. The heater includes a heating element with a first end and a second end and, between the first and second ends, different portions with different cross-sectional areas. The heating element further includes first and second terminals at the first and second ends, respectively. Current flowing through the heating element between the first and second terminals causes the heating element to generate heat. However, due to the different cross-sectional areas of the different portions, the current densities through those different portions are different and, thus, the different portions of the heating element generate different amounts of heat per unit length. The heating element can be designed and placed on-chip to facilitate local thermal tuning of different regions of a device or of different devices without requiring multiple different heating elements within a relatively small chip area. Also disclosed is an associated method.
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公开(公告)号:US11934021B2
公开(公告)日:2024-03-19
申请号:US17649191
申请日:2022-01-27
Applicant: GlobalFoundries U.S. Inc.
Inventor: Hemant Martand Dixit , William J. Taylor, Jr. , Yusheng Bian , Theodore Letavic , Oscar D. Restrepo
CPC classification number: G02B6/4269 , G02B6/122 , G02B6/125 , G02B2006/12135 , G02B2006/12142
Abstract: The disclosed subject matter relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to photonic devices having thermally conductive layers for the removal of heat from optoelectronic components in the photonic devices.
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公开(公告)号:US11387353B2
公开(公告)日:2022-07-12
申请号:US16907600
申请日:2020-06-22
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Jagar Singh , Sudarshan Narayanan , Alvin J. Joseph , William J. Taylor, Jr. , Jeffrey B. Johnson
IPC: H01L29/68 , H01L29/08 , H01L29/06 , H01L29/10 , H01L27/112
Abstract: A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.
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