公开(公告)号：US11456384B2

公开(公告)日：2022-09-27

申请号：US16921068

申请日：2020-07-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Wang Zheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49

Abstract: A structure includes a semiconductor fin; a first source/drain region and a second source/drain region in the semiconductor fin; a first doping region about the first source/drain region, defining a channel region in the semiconductor fin; and a second doping region about the second source/drain region, defining a drain extension in the semiconductor fin. A gate structure is over the channel region and the drain extension. The gate structure includes a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, and a contiguous gate conductor over the first metal layer and the second metal layer. One of the metal layers is over the channel region and the other is over the drain extension. The metal layers may have different thicknesses and/or work functions, to improve transconductance and RF performance of an LDMOS FinFET including the structure.

公开(公告)号：US20220005952A1

公开(公告)日：2022-01-06

申请号：US16921068

申请日：2020-07-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Wang Zheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A structure includes a semiconductor fin; a first source/drain region and a second source/drain region in the semiconductor fin; a first doping region about the first source/drain region, defining a channel region in the semiconductor fin; and a second doping region about the second source/drain region, defining a drain extension in the semiconductor fin. A gate structure is over the channel region and the drain extension. The gate structure includes a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, and a contiguous gate conductor over the first metal layer and the second metal layer. One of the metal layers is over the channel region and the other is over the drain extension. The metal layers may have different thicknesses and/or work functions, to improve transconductance and RF performance of an LDMOS FinFET including the structure.

公开(公告)号：US11545575B2

公开(公告)日：2023-01-03

申请号：US16919225

申请日：2020-07-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wenjun Li ,  Sudarshan Narayanan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extent and a second longitudinal extent. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first longitudinal extent and the second longitudinal extent, a first subfin portion under the upper fin portion in the first longitudinal extent having a first lateral dimension, and a second subfin portion under the upper fin portion in the second longitudinal extent having a second lateral dimension different than the first lateral dimension. The second subfin may be used in a drain extension region of a laterally-diffused metal-oxide semiconductor (LDMOS) device. The second subfin reduces subfin current and improves HCI reliability, regardless of the type of LDMOS device.

公开(公告)号：US11387353B2

公开(公告)日：2022-07-12

申请号：US16907600

申请日：2020-06-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Alvin J. Joseph ,  William J. Taylor, Jr. ,  Jeffrey B. Johnson

IPC: H01L29/68 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L27/112

Abstract: A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.

公开(公告)号：US20220005954A1

公开(公告)日：2022-01-06

申请号：US16919225

申请日：2020-07-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wenjun Li ,  Sudarshan Narayanan

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extent and a second longitudinal extent. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first longitudinal extent and the second longitudinal extent, a first subfin portion under the upper fin portion in the first longitudinal extent having a first lateral dimension, and a second subfin portion under the upper fin portion in the second longitudinal extent having a second lateral dimension different than the first lateral dimension. The second subfin may be used in a drain extension region of a laterally-diffused metal-oxide semiconductor (LDMOS) device. The second subfin reduces subfin current and improves HCI reliability, regardless of the type of LDMOS device.

公开(公告)号：US20210399116A1

公开(公告)日：2021-12-23

申请号：US16907600

申请日：2020-06-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Alvin J. Joseph ,  William J. Taylor, JR. ,  Jeffrey B. Johnson

IPC: H01L29/68 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

Abstract: A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.

公开(公告)号：US11164978B2

公开(公告)日：2021-11-02

申请号：US16774482

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Sudarshan Narayanan

IPC: H01L29/861 ,  H01L27/08 ,  H01L29/06 ,  H01L29/08

Abstract: A device includes a substrate having a top surface and a bottom surface. A first doping well having a first part and a second part is located in the substrate. An undoped moat is in the substrate between the first doping well and a second doping well. A diode includes an anode with an increased first doping concentration region in the first doping well and a cathode with an increased second doping concentration region in the second doping well. An isolation region is in the first doping well having a first portion proximate the top surface and a second portion distal to the top surface. A gap made of an undoped region is in the first doping well between the first part and the second part. The gap is located between the distal portion of the isolation region and the bottom surface of the substrate.

公开(公告)号：US20210234052A1

公开(公告)日：2021-07-29

申请号：US16774482

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jagar Singh ,  Sudarshan Narayanan

IPC: H01L29/861 ,  H01L29/08 ,  H01L29/06 ,  H01L27/08

Abstract: A device includes a substrate having a top surface and a bottom surface. A first doping well having a first part and a second part is located in the substrate. An undoped moat is in the substrate between the first doping well and a second doping well. A diode includes an anode with an increased first doping concentration region in the first doping well and a cathode with an increased second doping concentration region in the second doping well. An isolation region is in the first doping well having a first portion proximate the top surface and a second portion distal to the top surface. A gap made of an undoped region is in the first doping well between the first part and the second part. The gap is located between the distal portion of the isolation region and the bottom surface of the substrate.