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1.发明授权公开(公告)号：US08679919B2
公开(公告)日：2014-03-25
申请号：US13327361
申请日：2011-12-15
IPC分类号： H01L29/94
CPC分类号： H01L29/7827 , H01L21/2815 , H01L29/0634 , H01L29/407 , H01L29/41766 , H01L29/42376 , H01L29/66659 , H01L29/66689 , H01L29/66696 , H01L29/7816 , H01L29/7835
摘要： An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.
摘要翻译： 电子器件可以包括覆盖衬底并具有主表面和厚度的半导体层，其中沟槽延伸穿过半导体层厚度的至少大约50％的深度。 电子器件还可以包括在沟槽内的导电结构，其中导电结构延伸至沟槽深度的至少约50％。 电子器件还可以进一步包括在半导体层内的垂直取向的掺杂区域，该掺杂区域与导电结构相邻并与导电结构电绝缘; 以及设置在垂直取向的掺杂区域和导电结构之间的绝缘层。 形成电子器件的过程可以包括图案化半导体层以限定延伸穿过至少大约50％的半导体层的厚度的沟槽，并且在图案化半导体层以形成沟槽之后形成垂直取向的掺杂区域。
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2.发明申请ELECTRONIC DEVICE COMPRISING CONDUCTIVE STRUCTURES AND AN INSULATING LAYER BETWEEN THE CONDUCTIVE STRUCTURES AND WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME 有权导电结构的电子装置和导电结构之间的绝缘层以及其形成过程中的导电结构和绝缘层公开(公告)号：US20130153991A1
公开(公告)日：2013-06-20
申请号：US13327390
申请日：2011-12-15
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/41741 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/42376 , H01L29/456 , H01L29/4933 , H01L29/66659 , H01L29/66689 , H01L29/66696 , H01L29/7816 , H01L29/7827 , H01L29/7835
摘要： An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow RDSON to be lower for a given BVDSS.
摘要翻译： 电子器件可以包括包括下面的掺杂区域和覆盖衬底的半导体层的衬底。 沟槽可以具有侧壁并且至少部分地延伸穿过半导体层。 电子器件还可以包括邻近下面的掺杂区域的第一导电结构，绝缘层和沟槽内的第二导电结构。 绝缘层可以设置在第一和第二导电结构之间，并且第一导电结构可以设置在绝缘层和下面的掺杂区域之间。 可以执行形成电子器件的工艺，使得第一导电结构包括导电填充材料或半导体层内的掺杂区域。 第一导电结构可以允许下面的掺杂区域离沟道区域更远，并允许给定BVDSS的RDSON较低。
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3.发明授权公开(公告)号：US08647970B2
公开(公告)日：2014-02-11
申请号：US13327390
申请日：2011-12-15
IPC分类号： H01L21/425
CPC分类号： H01L29/41741 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/42376 , H01L29/456 , H01L29/4933 , H01L29/66659 , H01L29/66689 , H01L29/66696 , H01L29/7816 , H01L29/7827 , H01L29/7835
摘要： An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow RDSON to be lower for a given BVDSS.
摘要翻译： 电子器件可以包括包括下面的掺杂区域和覆盖衬底的半导体层的衬底。 沟槽可以具有侧壁并且至少部分地延伸穿过半导体层。 电子器件还可以包括邻近下面的掺杂区域的第一导电结构，绝缘层和沟槽内的第二导电结构。 绝缘层可以设置在第一和第二导电结构之间，并且第一导电结构可以设置在绝缘层和下面的掺杂区域之间。 可以执行形成电子器件的工艺，使得第一导电结构包括导电填充材料或半导体层内的掺杂区域。 第一导电结构可以允许下面的掺杂区域离沟道区域更远，并允许给定BVDSS的RDSON较低。
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4.发明申请ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME 有权包含导电结构的导体结构的电子器件和在其中的绝缘层及其形成方法公开(公告)号：US20130153987A1
公开(公告)日：2013-06-20
申请号：US13327361
申请日：2011-12-15
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/2815 , H01L29/0634 , H01L29/407 , H01L29/41766 , H01L29/42376 , H01L29/66659 , H01L29/66689 , H01L29/66696 , H01L29/7816 , H01L29/7835
摘要： An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.
摘要翻译： 电子器件可以包括覆盖衬底并具有主表面和厚度的半导体层，其中沟槽延伸穿过半导体层厚度的至少大约50％的深度。 电子器件还可以包括在沟槽内的导电结构，其中导电结构延伸至沟槽深度的至少约50％。 电子器件还可以进一步包括在半导体层内的垂直取向的掺杂区域，该掺杂区域与导电结构相邻并与导电结构电绝缘; 以及设置在垂直取向的掺杂区域和导电结构之间的绝缘层。 形成电子器件的过程可以包括图案化半导体层以限定延伸穿过至少大约50％的半导体层的厚度的沟槽，并且在图案化半导体层以形成沟槽之后形成垂直取向的掺杂区域。
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公开(公告)号：US08928050B2
公开(公告)日：2015-01-06
申请号：US13794103
申请日：2013-03-11
CPC分类号： H01L27/0255 , H01L29/063 , H01L29/1095 , H01L29/4175 , H01L29/7816 , H01L29/7824 , H01L29/872
摘要： An electronic device can include a semiconductor layer having a primary surface, and a Schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess. In other embodiment, the Schottky contact may not be formed within a recess, and a doped region may be formed within the semiconductor layer under the horizontally-oriented lightly doped region and have a conductivity type opposite the horizontally-oriented lightly doped region. The Schottky contacts can be used in conjunction with power transistors in a switching circuit, such as a high-frequency voltage regulator.
摘要翻译： 电子器件可以包括具有主表面的半导体层和包含与半导体层内的水平取向的轻掺杂区域接触并且位于主表面附近的含金属元件的肖特基接触。 在一个实施例中，含金属的构件位于半导体层中的凹部内，并沿凹槽的侧壁接触水平取向的轻掺杂区域。 在另一实施例中，肖特基接触可以不形成在凹槽内，并且可以在水平取向的轻掺杂区域之下的半导体层内形成掺杂区域，并且具有与水平取向的轻掺杂区域相反的导电类型。 肖特基触点可以与开关电路中的功率晶体管一起使用，例如高频电压调节器。
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公开(公告)号：US20140252484A1
公开(公告)日：2014-09-11
申请号：US13794103
申请日：2013-03-11
IPC分类号： H01L27/02
CPC分类号： H01L27/0255 , H01L29/063 , H01L29/1095 , H01L29/4175 , H01L29/7816 , H01L29/7824 , H01L29/872
摘要： An electronic device can include a semiconductor layer having a primary surface, and a Schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess. In other embodiment, the Schottky contact may not be formed within a recess, and a doped region may be formed within the semiconductor layer under the horizontally-oriented lightly doped region and have a conductivity type opposite the horizontally-oriented lightly doped region. The Schottky contacts can be used in conjunction with power transistors in a switching circuit, such as a high-frequency voltage regulator.
摘要翻译： 电子器件可以包括具有主表面的半导体层和包含与半导体层内的水平取向的轻掺杂区域接触并且位于主表面附近的含金属元件的肖特基接触。 在一个实施例中，含金属的构件位于半导体层中的凹部内，并沿凹槽的侧壁接触水平取向的轻掺杂区域。 在另一实施例中，肖特基接触可以不形成在凹槽内，并且可以在水平取向的轻掺杂区域之下的半导体层内形成掺杂区域，并且具有与水平取向的轻掺杂区域相反的导电类型。 肖特基触点可以与开关电路中的功率晶体管一起使用，例如高频电压调节器。
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公开(公告)号：US09048214B2
公开(公告)日：2015-06-02
申请号：US13590947
申请日：2012-08-21
IPC分类号： H01L29/66 , H01L29/40 , H01L29/78 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/404 , H01L29/407 , H01L29/42368 , H01L29/66734
摘要： In one embodiment, a structure for a semiconductor device has trench shield electrodes formed above and below a gate electrode. The structure can be configured to function as a bidirectional power field effect transistor.
摘要翻译： 在一个实施例中，半导体器件的结构具有形成在栅极电极上方和下方的沟槽屏蔽电极。 该结构可以被配置为用作双向功率场效应晶体管。
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公开(公告)号：US20140084363A1
公开(公告)日：2014-03-27
申请号：US13627912
申请日：2012-09-26
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42372 , H01L29/4238 , H01L29/4933 , H01L29/66734 , H01L29/7811
摘要： In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.
摘要翻译： 在一个实施例中，MOS晶体管形成为具有有源区和端接区。 在终止区域内，形成多个导体以与多个沟槽内的导体电接触。 终端区域中的多个导体形成为基本共面。
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9.发明申请PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN 有权形成电子装置的方法，包括TRENCH和导电结构公开(公告)号：US20130221428A1
公开(公告)日：2013-08-29
申请号：US13404855
申请日：2012-02-24
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence.
摘要翻译： 电子器件可以包括晶体管结构，其包括覆盖在衬底上并具有主表面的图案化半导体层，其中图案化的半导体层限定从主表面朝向衬底延伸的第一沟槽和第二沟槽。 电子器件还可以包括在第一沟槽内的第一导电电极和栅电极。 电子器件还可以在第二沟槽内进一步包括第二导电电极。 电子器件可以包括图案化半导体层内的源极区域，并且设置在第一和第二沟槽之间。 电子器件还可以包括在图案化的半导体层内以及在第一和第二沟槽之间的体接触区域，其中主体接触区域与主表面间隔开。 形成电子器件的过程可以利用在处理序列期间形成所有沟槽的优点。
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公开(公告)号：US08415739B2
公开(公告)日：2013-04-09
申请号：US12271106
申请日：2008-11-14
申请人： Prasad Venkatraman , Zia Hossain
发明人： Prasad Venkatraman , Zia Hossain
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor component that includes an edge termination structure and a method of manufacturing the semiconductor component. A semiconductor material has a semiconductor device region and an edge termination region. One or more device trenches may be formed in the semiconductor device region and one or more termination trenches is formed in the edge termination region. A source electrode is formed in a portion of a termination trench adjacent its floor and a floating electrode termination structure is formed in the portion of the termination trench adjacent its mouth. A second termination trench may be formed in the edge termination region and a non-floating electrode may be formed in the second termination trench. Alternatively, the second termination trench may be omitted and a trench-less non-floating electrode may be formed in the edge termination region.
摘要翻译： 一种包括边缘终端结构的半导体部件和制造半导体部件的方法。 半导体材料具有半导体器件区域和边缘终止区域。 一个或多个器件沟槽可以形成在半导体器件区域中，并且在边缘终止区域中形成一个或多个端接沟槽。 源极电极形成在靠近其底板的终端沟槽的一部分中，并且在靠近其端口的端接沟槽的部分中形成浮动电极端接结构。 可以在边缘终止区域中形成第二终止沟槽，并且可以在第二终端沟槽中形成非浮置电极。 或者，可以省略第二终端沟槽，并且可以在边缘终止区域中形成无沟槽非浮动电极。
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