摘要:
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.
摘要:
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.
摘要:
A self-synchronizing data bus analyser is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.
摘要:
A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.
摘要:
The present invention relates to an electric power supply circuit (1) for a turbojet engine nacelle including at least one electric generator (2) mechanically connected to the shaft of a turbojet engine, said generator being capable of directly supplying electric power to a first electric power device other than a simple monitoring or supervising unit, characterized in that said generator is capable of directly supplying electric power to at least one second electric power device other than a monitoring or supervising unit, as well as to a nacelle including such an electric circuit.
摘要:
An automated method and system for refunding the unused portion of an electronic ticket are provided. In accordance with the method, an aging period is set and is added to the scheduled departure date of the issued ticket. If the schedules departure date plus the aging date is earlier than the current date, a determination is made as to whether the ticket has been used. If the ticket has not been used, the residual value of the ticket is calculated and a refund is issued.
摘要:
The invention relates to novel hemoglobin compositions, particularly novel recombinant mutant hemoglobin compositions, which eliminate or substantially reduce 1) the creation of heart lesions, 2) gastrointestinal discomfort, 3) pressor effects, and 4) endotoxin hypersensitivity associated with the administration of extracellular hemoglobin compositions in various therapeutic applications. Applications described include treatments for anemia, head injury, hemorrhage or hypovolemia, ischemia, cachexia, sickle cell crisis and stroke; enhancing cancer treatments; stimulating hematopoiesis; improving repair of physically damaged tissues; alleviating cardiogenic shock; and shock resuscitation.
摘要:
A nacelle for a turbojet engine includes an air inlet forward section, a median section surrounding a fan of the turbojet engine, an aft section equipped with a thrust reverser system, a power control unit able to convert a high voltage electric supply into an electric supply towards an electromechanical actuator, and a drive unit for the power control unit which is distinct and separate from the latter and has a control input and a drive output to be connected to the power control unit. The thrust reverser system includes a mobile cowl which, under action of an electromechanical actuator, is able to move from a closed position to an open position in which the mobile cowl opens a passage in the nacelle.
摘要:
A nacelle for receiving an aircraft engine, the nacelle having a tubular stationary cover and at least one movable portion connected to the stationary cover via movement means for moving the movable portion between a position close to the stationary cover and a position spaced apart therefrom. The movement means have asynchronous motors, each having a stator with windings connected in parallel to a power supply circuit and a rotor having windings, each connected to a resistive load in parallel with a winding of the rotor of each of the other motors.
摘要:
An alignment circuit is configured to receive a reference clock signal (ref_clk) derived from a main clock having a period T and successive sets of 2n data bits that are transmitted in parallel on a data bus wherein said data bits are aligned with respect to said reference clock signal but misaligned with respect to each other. It first comprises a plurality of n aligners. Each aligner is coupled to said reference clock and a pair of said data bits, referred to as primary bits, one data bit (bit_tdat(i)) having the rank (i) in a determined set and the other being the corresponding data bit (bit_tdat(i+n)) having the rank (i+n) in the set. Each aligner comprises first, second and third shifting means for shifting said primary data bits to respectively generate respective data bits delayed of one, two and two and half cycles and a multiplexor receiving said primary and delayed data bits under the control of three control signals of a first type (recal(i), realign0(i) and realign1(i)) to generate a pair of aligned data bits (tdat_desk(i) & tdat_desk(i+n)).