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公开(公告)号:US20180081816A1
公开(公告)日:2018-03-22
申请号:US15273433
申请日:2016-09-22
Applicant: Google Inc.
Inventor: Joel Dylan Coburn , Albert Borchers , Christopher Lyle Johnson , Robert S. Sprinkle
IPC: G06F12/0868 , G06F12/0871 , G06F12/0873 , G06F12/12 , G06F12/1009 , G06F12/1027
CPC classification number: G06F12/0868 , G06F12/023 , G06F12/04 , G06F12/0815 , G06F12/0871 , G06F12/0873 , G06F12/1009 , G06F12/1027 , G06F12/12 , G06F2212/1016 , G06F2212/1024 , G06F2212/152 , G06F2212/3042 , G06F2212/305 , G06F2212/604 , G06F2212/652
Abstract: Methods, systems, and apparatus for receiving a request to access, from a main memory, data contained in a first portion of a first page of data, the first page of data having a first page size; initiating a page fault based on determining that the first page of data is not stored in the main memory; allocating a portion of the main memory equivalent to the first page size; transferring the first portion of the first page of data from the secondary memory to the allocated portion of the main memory without transferring the entire first page of data; and updating a first page table entry associated with the first portion of the first page of data to point to a location of the allocated portion of the main memory to which the first portion of the first page of data is transferred.
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公开(公告)号:US20180018123A1
公开(公告)日:2018-01-18
申请号:US15267404
申请日:2016-09-16
Applicant: Google Inc.
Inventor: Monish Shah , Benjamin Charles Serebrin , Albert Borchers
IPC: G06F3/06
CPC classification number: G06F3/0647 , G06F3/0611 , G06F3/0656 , G06F3/0685 , G06F12/08 , G06F12/0868 , G06F12/1081 , G06F13/28 , G06F2212/1024 , G06F2212/312
Abstract: IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.
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公开(公告)号:US20180046411A1
公开(公告)日:2018-02-15
申请号:US15236171
申请日:2016-08-12
Applicant: Google Inc.
Inventor: Joel Dylan Coburn , Albert Borchers , Christopher Lyle Johnson , Robert S. Sprinkle
IPC: G06F3/06 , G06F12/0815 , G06F12/0811
CPC classification number: G06F3/0685 , G06F3/0619 , G06F3/065 , G06F12/0811 , G06F12/0815 , G06F12/0835 , G06F12/0868 , G06F12/1009 , G06F12/1081 , G06F2212/1021 , G06F2212/283 , G06F2212/621
Abstract: Methods, systems, and apparatus for receiving a request to access, from a main memory, a first cache line of a page of data; determining that the first cache line is not stored in the main memory and is stored in a secondary memory, and in response: transferring the first cache line of the page of data from the secondary memory to the main memory without transferring the entire page of data, wherein a remaining portion of the page of data remains stored in the secondary memory; updating a page table entry associated with the page of data to point to a location of the page of data in the main memory; and transferring the remaining portion of the page of data from the secondary memory to the main memory.
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公开(公告)号:US20180046378A1
公开(公告)日:2018-02-15
申请号:US15235495
申请日:2016-08-12
Applicant: Google Inc.
Inventor: Joel Dylan Coburn , Albert Borchers , Christopher Lyle Johnson , Robert S. Sprinkle
IPC: G06F3/06 , G06F12/123 , G06F12/1009
CPC classification number: G06F12/1009 , G06F12/121 , G06F2212/1024 , G06F2212/1032 , G06F2212/152 , G06F2212/657
Abstract: Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.
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