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公开(公告)号：US11903329B2
公开(公告)日：2024-02-13
申请号：US17836893
申请日：2022-06-09
Applicant: Google LLC
Inventor： Brian James Burkett
CPC classification number: H10N60/0912 , B82Y10/00 , G06N10/00
Abstract: A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate, forming a first resist layer on the dielectric substrate, forming a second resist layer on the first resist layer, and forming a third resist layer on the second resist layer. The first resist layer includes a first opening extending through a thickness of the first resist layer, the second resist layer includes a second opening aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening aligned over the second opening and extending through a thickness of the third resist layer.
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公开(公告)号：US11662664B2
公开(公告)日：2023-05-30
申请号：US17856564
申请日：2022-07-01
Applicant: Google LLC
Inventor： Brian James Burkett , Rami Barends
CPC classification number: G03F7/70425 , G03F1/36 , G03F1/70 , G03F1/76
Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.
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公开(公告)号：US20200279990A1
公开(公告)日：2020-09-03
申请号：US16648101
申请日：2017-09-18
Applicant: Google LLC
Inventor： Brian James Burkett
Abstract: A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate (208), forming a first resist layer (210) on the dielectric substrate, forming a second resist layer (212) on the first resist layer, and forming a third resist layer (214) on the second resist layer. The first resist layer includes a first opening (216) extending through a thickness of the first resist layer, the second resist layer includes a second opening (218) aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening (220) aligned over the second opening and extending through a thickness of the third resist layer.
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公开(公告)号：US20230225223A1
公开(公告)日：2023-07-13
申请号：US18117918
申请日：2023-03-06
Applicant: Google LLC
Inventor： Brian James Burkett , Ofer Naaman , Anthony Edward Megrant , Theodore Charles White
CPC classification number: H10N60/0912 , G06N10/00 , H10N60/12 , H10N60/805
Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.
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公开(公告)号：US20230119165A1
公开(公告)日：2023-04-20
申请号：US17856564
申请日：2022-07-01
Applicant: Google LLC
Inventor： Brian James Burkett , Rami Barends
Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.
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Patent Agency Ranking
公开(公告)号：US10990017B2
公开(公告)日：2021-04-27
申请号：US16325319
申请日：2017-12-01
Applicant: Google LLC
Inventor： Brian James Burkett , Rami Barends
Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.
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公开(公告)号：US20240047277A1
公开(公告)日：2024-02-08
申请号：US17883475
申请日：2022-08-08
Applicant: Google LLC
Inventor： Brian James Burkett
CPC classification number: H01L22/12 , H01L39/2493 , H01L21/67225
Abstract: A method includes: forming an opening in a mask layer; measuring a feature size associated with a dimension of the opening; based on the feature size, determining a fabrication parameter; and forming a second layer in the opening. Forming the second layer is based on the fabrication parameter. A fabrication system includes a lithography system; a measurement system; a physical vapor deposition system; an oxidation system; and a control system. The control system is configured to control a feed-forward fabrication process.
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公开(公告)号：US20230114700A1
公开(公告)日：2023-04-13
申请号：US17962144
申请日：2022-10-07
Applicant: Google LLC
Inventor： Brian James Burkett , John Mark Kreikebaum
IPC: H01L21/308 , H01L21/324 , H01L21/02 , H01L21/3205
Abstract: A substrate, a first layer disposed on the substrate, and a second layer disposed on the first layer are provided. An opening is etched through the second layer to the first layer. A first portion of the first layer is etched through the opening using a first etchant, to expose a surface of the substrate through the opening. A feature is deposited on the surface of the substrate through the opening. A second portion of the first layer is etched using a gaseous etchant, to release the substrate from the second layer.
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公开(公告)号：US11600763B2
公开(公告)日：2023-03-07
申请号：US16964053
申请日：2019-07-25
Applicant: Google LLC
Inventor： Brian James Burkett , Ofer Naaman , Anthony Edward Megrant , Theodore Charles White
Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.
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公开(公告)号：US11588094B2
公开(公告)日：2023-02-21
申请号：US16648101
申请日：2017-09-18
Applicant: Google LLC
Inventor： Brian James Burkett
Abstract: A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate (208), forming a first resist layer (210) on the dielectric substrate, forming a second resist layer (212) on the first resist layer, and forming a third resist layer (214) on the second resist layer. The first resist layer includes a first opening (216) extending through a thickness of the first resist layer, the second resist layer includes a second opening (218) aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening (220) aligned over the second opening and extending through a thickness of the third resist layer.
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