公开(公告)号：US12216587B2

公开(公告)日：2025-02-04

申请号：US18583341

申请日：2024-02-21

Applicant: Google LLC

Inventor： Jiazhen Zheng ,  Srinivas Vaduvatha ,  Hugh McEvoy Walsh ,  Prashant R. Chandra ,  Abhishek Agarwal ,  Weihuang Wang ,  Weiwei Jiang

IPC: G06F12/0895 ,  G06F12/0864 ,  G06F12/121

Abstract: A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.

公开(公告)号：US20240235710A9

公开(公告)日：2024-07-11

申请号：US17969095

申请日：2022-10-19

Applicant: Google LLC

Inventor： Abhishek Agarwal ,  Ye Tang ,  Prashant R. Chandra ,  Simon Luigi Sabato ,  Hema Hariharan

IPC: H04J3/06

CPC classification number: H04J3/0667

Abstract: Aspects of the disclosure are directed to supporting time synchronization across a datacenter network with greater accuracy. The time synchronization includes both software based and hardware based time synchronization mechanisms to provide more precise time synchronization across various nodes in the datacenter network. The software based mechanism can provide the initial coarse time synchronization while the hardware based mechanism can provide the subsequent finer time synchronization.

公开(公告)号：US20240048277A1

公开(公告)日：2024-02-08

申请号：US17879853

申请日：2022-08-03

Applicant: Google LLC

Inventor： Yuliang Li ,  Hassan Mohamed Gamal Hassan Wassel ,  Behnam Montazeri ,  Weihuang Wang ,  Srinivas Vaduvatha ,  Nandita Dukkipati ,  Prashant R. Chandra ,  Masoud Moshref Javadi

IPC: H04L1/16 ,  H04L1/18 ,  H04L43/106

CPC classification number: H04L1/1671 ,  H04L1/189 ,  H04L43/106

Abstract: The technology is directed to the use of a bitmap generated at a receiver to track the status of received packets sent by a transmitter. The technology may include a network device including an input port, output port, and circuitry. The circuitry may generate a transmitter bitmap that tracks each data packet sent to another network device. The circuitry of the network device may receive, from the other network device, a receiver bitmap that identifies each data packet that is received and not received from the network device. The circuitry may then determine which data packets to retransmit by comparing the transmitter bitmap to the receiver bitmap.

公开(公告)号：US11765081B2

公开(公告)日：2023-09-19

申请号：US17890348

申请日：2022-08-18

Applicant: Google LLC

Inventor： Prashant R. Chandra ,  Balakrishna Raghunath ,  Uday Ramakrishna Naik ,  Michael Dalton

IPC: H04L45/64 ,  H04L45/586 ,  G06F9/455 ,  H04L45/745 ,  H04L69/22 ,  H04L61/5007

CPC classification number: H04L45/586 ,  G06F9/45558 ,  H04L45/64 ,  H04L45/745 ,  H04L61/5007 ,  H04L69/22 ,  G06F2009/45595

Abstract: Systems and methods of offloading multicast virtual network packet processing to a network interface card are provided. In an example implementation, a network interface card can route packets in a virtual network. The network interface card can be configured to receive a data packet having a multicast header for transmission to a plurality of destination virtual machines. The network interface card can retrieve a list of next hop destinations for the data packet. The network interface card can replicate the packet for each next hop destination. The network interface card can encapsulate each replicated packet with a unicast header that includes a next hop destination virtual IP address indicating the next hop destination and a source virtual IP address, and transmit the encapsulated packets.

公开(公告)号：US12199746B2

公开(公告)日：2025-01-14

申请号：US17969095

申请日：2022-10-19

Applicant: Google LLC

Inventor： Abhishek Agarwal ,  Ye Tang ,  Prashant R. Chandra ,  Simon Luigi Sabato ,  Hema Hariharan

IPC: H04J3/06

Abstract: Aspects of the disclosure are directed to supporting time synchronization across a datacenter network with greater accuracy. The time synchronization includes both software based and hardware based time synchronization mechanisms to provide more precise time synchronization across various nodes in the datacenter network. The software based mechanism can provide the initial coarse time synchronization while the hardware based mechanism can provide the subsequent finer time synchronization.

公开(公告)号：US20230393987A1

公开(公告)日：2023-12-07

申请号：US17834018

申请日：2022-06-07

Applicant: Google LLC

Inventor： Jiazhen Zheng ,  Srinivas Vaduvatha ,  Hugh McEvoy Walsh ,  Prashant R. Chandra ,  Abhishek Agarwal ,  Weihuang Wang ,  Weiwei Jiang

IPC: G06F12/0895 ,  G06F12/0864 ,  G06F12/121

CPC classification number: G06F12/0895 ,  G06F12/0864 ,  G06F12/121

Abstract: A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.

公开(公告)号：US20230267089A1

公开(公告)日：2023-08-24

申请号：US18112740

申请日：2023-02-22

Applicant: Google LLC

Inventor： Santanu Dasgupta ,  Durgaprasad V. Ayyadevara ,  Bor Chan ,  Prashant R. Chandra ,  Bok Knun Randolph Chung ,  Max Kamenetsky ,  Rajeev Koodli ,  Shahin Valoth

IPC: G06F13/38 ,  G06F13/12

CPC classification number: G06F13/385 ,  G06F13/122 ,  G06F2213/0038

Abstract: The present disclosure provides a compute platform architecture for virtualized and cloud native network functions. The architecture uses a reduced instruction set computer-based general purpose processor along with multiple special purpose accelerators and an integrated network interface card. As such, the architecture can accommodate multiple hundreds of gigabits of input/output.

公开(公告)号：US20240137140A1

公开(公告)日：2024-04-25

申请号：US17969095

申请日：2022-10-18

Applicant: Google LLC

Inventor： Abhishek Agarwal ,  Ye Tang ,  Prashant R. Chandra ,  Simon Luigi Sabato ,  Hema Hariharan

IPC: H04J3/06

CPC classification number: H04J3/0667

Abstract: Aspects of the disclosure are directed to supporting time synchronization across a datacenter network with greater accuracy. The time synchronization includes both software based and hardware based time synchronization mechanisms to provide more precise time synchronization across various nodes in the datacenter network. The software based mechanism can provide the initial coarse time synchronization while the hardware based mechanism can provide the subsequent finer time synchronization.

公开(公告)号：US20230394082A1

公开(公告)日：2023-12-07

申请号：US17833126

申请日：2022-06-06

Applicant: Google LLC

Inventor： Weiwei Jiang ,  Srinivas Vaduvatha ,  Prashant R. Chandra ,  Jiazhen Zheng ,  Hugh McEvoy Walsh ,  Weihuang Wang ,  Abhishek Agarwal

IPC: G06F3/06 ,  G06F16/901

CPC classification number: G06F3/0659 ,  G06F16/9014 ,  G06F16/9017 ,  G06F3/0613 ,  G06F3/0673

Abstract: A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.

公开(公告)号：US11824954B2

公开(公告)日：2023-11-21

申请号：US17857620

申请日：2022-07-05

Applicant: Google LLC

Inventor： Weihuang Wang ,  Prashant R. Chandra ,  Srinivas Vaduvatha

IPC: H04L67/55 ,  H04L1/1829

CPC classification number: H04L67/55 ,  H04L1/1832

Abstract: A communication protocol system is provided for reliable transport of packets. Transport of packets includes transmitting, by a sender entity over a connection to a receiver entity, a plurality of packets in a first order, maintaining, by the sender entity, one or more sliding windows including a plurality of bits, wherein each bit of the sliding window represents a respective packet of the plurality of packets, receiving, by the sender entity, one or more acknowledgments indicating that one or more of the plurality of packets have been received by the receiver entity, each of the acknowledgments referencing a respective packet of the plurality of packets and modifying, by the sender entity, values of one or more of the plurality of bits in the sliding window corresponding to the one or more acknowledgments received.