-
公开(公告)号:US10482940B2
公开(公告)日:2019-11-19
申请号:US16062578
申请日:2015-12-17
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Miao Hu , John Paul Strachan , Zhiyong Li , Stanley Williams
Abstract: Example implementations of the present disclosure relate to improved computational accuracy in a crossbar array. An example system may include a crossbar array, having a plurality of memory elements at junctions, usable in performance of computations. The example system may further include a calculate engine to calculate ideal conductance of memory elements at a plurality of junctions of the crossbar array and a determine engine to determine conductance of the memory elements at the plurality of junctions of the crossbar array. An adjust engine of the example system may be used to adjust conductance of at least one memory element to improve computational accuracy by reduction of a difference between the ideal conductance and the determined conductance of the at least one memory element.
-
公开(公告)号:US10262733B2
公开(公告)日:2019-04-16
申请号:US15325543
申请日:2014-10-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Jianhua Yang , Miao Hu , John Paul Strachan , Ning Ge
Abstract: A memristive dot-product system for vector processing is described. The memristive dot-product system includes a crossbar array having a number of memory elements. Each memory element includes a memristor. Each memory element includes a transistor. The system also includes a vector input register. The system also includes a vector output register.
-
公开(公告)号:US10109348B2
公开(公告)日:2018-10-23
申请号:US15522364
申请日:2014-10-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Miao Hu , Jianhua Yang , John Paul Strachan , Ning Ge
Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.
-
公开(公告)号:US09847124B2
公开(公告)日:2017-12-19
申请号:US15500500
申请日:2015-04-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Miao Hu , John Paul Strachan , Ning Ge , Jianhua Yang
CPC classification number: G11C13/0021 , G06F7/588 , G06F17/18 , G06G7/122 , G06N7/005
Abstract: An example apparatus includes a crossbar array of signal lines and control lines. The example apparatus also includes an input controller in circuit with the control lines. The input control is to select one of the control lines. The example apparatus also includes first resistive elements connected between corresponding ones of the control lines and corresponding ones of the signal lines. The first resistive elements have first conductances set to operate as a matrix of probabilities that define a fixed transition kernel of a Markov Chain. The example apparatus also includes second resistive elements in circuit with the signal lines. The second resistive elements have second conductances set to select one of the signal lines exclusive of others of the signal lines based on a subset of the probabilities in the matrix of the probabilities.
-
公开(公告)号:US09842646B2
公开(公告)日:2017-12-12
申请号:US15500555
申请日:2015-04-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Miao Hu , Ning Ge , John Paul Strachan , R. Stanley Williams
CPC classification number: G11C13/004 , G06N3/049 , G06N3/0635 , G11C11/54 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C27/005 , G11C2213/74 , G11C2213/75 , G11C2213/76 , G11C2213/79
Abstract: In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In addition, application of a reading voltage across the second memristor is delayed by a time period equivalent to the programmed resistance level of the first memristor and the capacitance of the capacitor.
-
公开(公告)号:US20170221558A1
公开(公告)日:2017-08-03
申请号:US15500555
申请日:2015-04-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Miao Hu , Ning Ge , John Paul Strachan , R. Stanley Williams
IPC: G11C13/00
CPC classification number: G11C13/004 , G06N3/049 , G06N3/0635 , G11C11/54 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C27/005 , G11C2213/74 , G11C2213/75 , G11C2213/76 , G11C2213/79
Abstract: In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In addition, application of a reading voltage across the second memristor is delayed by a time period equivalent to the programmed resistance level of the first memristor and the capacitance of the capacitor.
-
公开(公告)号:US10580473B2
公开(公告)日:2020-03-03
申请号:US16283513
申请日:2019-02-22
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Ning Ge , John Paul Strachan , Jianhua Yang , Miao Hu
Abstract: A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.
-
公开(公告)号:US20190035463A1
公开(公告)日:2019-01-31
申请号:US16148468
申请日:2018-10-01
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Miao Hu , Jianhua Yang , John Paul Strachan , Ning Ge
Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.
-
公开(公告)号:US20180350433A1
公开(公告)日:2018-12-06
申请号:US15570980
申请日:2015-09-25
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Miao Hu , Zhiyong Li , John Paul Strachan
CPC classification number: G11C13/0007 , G06G7/16 , G11C5/05 , G11C13/0023 , G11C13/003 , G11C13/0069 , G11C2213/79
Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
-
公开(公告)号:US20180301189A1
公开(公告)日:2018-10-18
申请号:US15570932
申请日:2015-08-07
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Miao Hu , John Paul Strachan , Zhiyong Li , R. Stanley Williams
Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, and a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections. Each junction comprises a resistive memory element, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
-
-
-
-
-
-
-
-
-