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    Power sense output
    2.
    发明授权
    Power sense output 有权

    公开(公告)号：US10520530B2

    公开(公告)日：2019-12-31

    申请号：US15661612

    申请日：2017-07-27

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Vincent W. Michna ,  Peter Hansen ,  Julie Victoria Tan

    IPC: G06F11/30 ,  G01R19/25

    Abstract: Examples disclosed herein relate to determining a power sense output based on a current sense line and a voltage sense line. A first stage circuit has a first voltage input of the current sense line of a server. The first stage circuit also has a feedback voltage input based on an output voltage of the first stage circuit and a variable resistance value based on the voltage sense line of the server. A second stage circuit is used to buffer the first output voltage to yield a second output voltage. A third stage circuit yields a power sense output based on a difference between the second output voltage and the first voltage input.

    DETERMINING A POWER CAPPING SIGNAL USING DIRECT MEMORY ACCESS
    3.
    发明申请
    DETERMINING A POWER CAPPING SIGNAL USING DIRECT MEMORY ACCESS 审中-公开

    公开(公告)号：US20180373303A1

    公开(公告)日：2018-12-27

    申请号：US15631734

    申请日：2017-06-23

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Peter Hansen ,  Julie Victoria Tan

    IPC: G06F1/32 ,  H03M1/50 ,  H03K7/08 ,  H03M1/00

    CPC classification number: G06F1/3206 ,  G06F1/3225 ,  H03K7/08 ,  H03M1/001 ,  H03M1/002 ,  H03M1/504

    Abstract: Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.

    Scalable universal sensor data acquisition with predictable timing
    5.
    发明授权
    Scalable universal sensor data acquisition with predictable timing 有权

    公开(公告)号：US11304344B2

    公开(公告)日：2022-04-12

    申请号：US16528423

    申请日：2019-07-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Nilashis Dey ,  Peter Hansen

    IPC: H05K7/20 ,  H04L67/125 ,  H05K7/14

    Abstract: A device that is communicating with other devices via a common bus discovers addresses of the other devices. The device transmits data to the other devices at a transmit time determined based on the addresses of the other devices. The device predicts receive times at which data will be received from the other devices and determines the transmit time based on predicted receive times, avoiding data collisions. The devices may include universal sensor data acquisition devices (“USDADs”) that are each connectable to different types of sensors arranged within a server rack. Each USDAD determines a type of a connected sensor that is within a server rack and collects sensor data from the connected sensor.

    Server updates
    6.
    发明授权
    Server updates 有权

    公开(公告)号：US10956143B2

    公开(公告)日：2021-03-23

    申请号：US15833666

    申请日：2017-12-06

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Suhas Shivanna ,  John Harsany ,  Peter Hansen

    IPC: G06F8/65

    Abstract: A method disclosed herein relates to determining an inventory of a plurality of servers based on unique fingerprints and common fingerprints; creating a common set of installed firmware and a plurality of unique sets of installed firmware based on the inventory of the plurality of servers; creating subcategory sets of installed firmware based on the common set of installed firmware and categories of components included in the plurality of servers; obtaining updated versions of firmware corresponding to the subcategory sets of installed firmware and the unique sets of installed firmware; in response to an update request, creating containers for the updated versions of firmware corresponding to the subcategory sets of the installed firmware and the unique sets of installed firmware; and sending update messages to the plurality of servers including links to the respective containers.

    SCALABLE UNIVERSAL SENSOR DATA ACQUISITION WITH PREDICTABLE TIMING
    8.
    发明申请
    SCALABLE UNIVERSAL SENSOR DATA ACQUISITION WITH PREDICTABLE TIMING 有权

    公开(公告)号：US20210037680A1

    公开(公告)日：2021-02-04

    申请号：US16528423

    申请日：2019-07-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Nilashis Dey ,  Peter Hansen

    IPC: H05K7/20 ,  H05K7/14 ,  H04L29/08

    Abstract: A device that is communicating with other devices via a common bus discovers addresses of the other devices. The device transmits data to the other devices at a transmit time determined based on the addresses of the other devices. The device predicts receive times at which data will be received from the other devices and determines the transmit time based on predicted receive times, avoiding data collisions. The devices may include universal sensor data acquisition devices (“USDADs”) that are each connectable to different types of sensors arranged within a server rack. Each USDAD determines a type of a connected sensor that is within a server rack and collects sensor data from the connected sensor.

    Determining a power capping signal using direct memory access
    9.
    发明授权
    Determining a power capping signal using direct memory access 有权

    公开(公告)号：US10725520B2

    公开(公告)日：2020-07-28

    申请号：US15631734

    申请日：2017-06-23

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Peter Hansen ,  Julie Victoria Tan

    IPC: G06F1/3206 ,  G06F1/3225 ,  H03M1/50 ,  H03K7/08 ,  H03M1/00

    Abstract: Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.

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