公开(公告)号：US20190033349A1

公开(公告)日：2019-01-31

申请号：US15661612

申请日：2017-07-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Vincent W. Michna ,  Peter Hansen ,  Julie Victoria Tan

IPC: G01R19/25

Abstract: Examples disclosed herein relate to determining a power sense output based on a current sense line and a voltage sense line. A first stage circuit has a first voltage input of the current sense line of a server. The first stage circuit also has a feedback voltage input based on an output voltage of the first stage circuit and a variable resistance value based on the voltage sense line of the server. A second stage circuit is used to buffer the first output voltage to yield a second output voltage. A third stage circuit yields a power sense output based on a difference between the second output voltage and the first voltage input.

公开(公告)号：US10725520B2

公开(公告)日：2020-07-28

申请号：US15631734

申请日：2017-06-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Peter Hansen ,  Julie Victoria Tan

IPC: G06F1/3206 ,  G06F1/3225 ,  H03M1/50 ,  H03K7/08 ,  H03M1/00

Abstract: Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.

公开(公告)号：US10520530B2

公开(公告)日：2019-12-31

申请号：US15661612

申请日：2017-07-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Vincent W. Michna ,  Peter Hansen ,  Julie Victoria Tan

IPC: G06F11/30 ,  G01R19/25

Abstract: Examples disclosed herein relate to determining a power sense output based on a current sense line and a voltage sense line. A first stage circuit has a first voltage input of the current sense line of a server. The first stage circuit also has a feedback voltage input based on an output voltage of the first stage circuit and a variable resistance value based on the voltage sense line of the server. A second stage circuit is used to buffer the first output voltage to yield a second output voltage. A third stage circuit yields a power sense output based on a difference between the second output voltage and the first voltage input.

公开(公告)号：US20180373303A1

公开(公告)日：2018-12-27

申请号：US15631734

申请日：2017-06-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Peter Hansen ,  Julie Victoria Tan

IPC: G06F1/32 ,  H03M1/50 ,  H03K7/08 ,  H03M1/00

CPC classification number: G06F1/3206 ,  G06F1/3225 ,  H03K7/08 ,  H03M1/001 ,  H03M1/002 ,  H03M1/504

Abstract: Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.