公开(公告)号：US20100163846A1

公开(公告)日：2010-07-01

申请号：US12319164

申请日：2008-12-31

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

公开(公告)号：US20130221430A1

公开(公告)日：2013-08-29

申请号：US13594837

申请日：2012-08-26

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

公开(公告)号：US07943989B2

公开(公告)日：2011-05-17

申请号：US12319164

申请日：2008-12-31

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

公开(公告)号：US09024375B2

公开(公告)日：2015-05-05

申请号：US13594837

申请日：2012-08-26

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L29/808 ,  H01L29/861 ,  H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

公开(公告)号：US08263482B2

公开(公告)日：2012-09-11

申请号：US13065880

申请日：2011-03-31

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

公开(公告)号：US20110183499A1

公开(公告)日：2011-07-28

申请号：US13065880

申请日：2011-03-31

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L21/20 ,  B82Y40/00

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

公开(公告)号：US20110147830A1

公开(公告)日：2011-06-23

申请号：US12643837

申请日：2009-12-21

申请人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/78 ,  H01L29/7811

摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.

摘要翻译： 公开了自对准电荷平衡半导体器件及其形成方法。 在第一导电类型的半导体衬底上形成一个或多个平面栅极。 在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。 沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

公开(公告)号：US08519476B2

公开(公告)日：2013-08-27

申请号：US12643837

申请日：2009-12-21

申请人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/78 ,  H01L29/7811

摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.

摘要翻译： 公开了自对准电荷平衡半导体器件及其形成方法。 在第一导电类型的半导体衬底上形成一个或多个平面栅极。 在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。 沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

公开(公告)号：US20170125514A9

公开(公告)日：2017-05-04

申请号：US14298922

申请日：2014-06-08

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

IPC分类号： H01L29/06 ,  H01L21/266 ,  H01L21/324 ,  H01L29/10

CPC分类号： H01L29/0634 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802

摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

公开(公告)号：US20150357406A1

公开(公告)日：2015-12-10

申请号：US14298922

申请日：2014-06-08

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

IPC分类号： H01L29/06 ,  H01L21/266 ,  H01L21/324 ,  H01L29/10

CPC分类号： H01L29/0634 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802

摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

摘要翻译： 本发明公开了一种在半导体基板上制造半导体功率器件的方法， 漂移区由外延层组成。 该方法包括：生长第一外延层，然后在外延层顶部形成第一硬掩模层的第一步骤; 第二步骤，施加第一注入掩模以打开多个植入窗口，并施加第二注入掩模以阻挡一些植入窗口，以在第一外延层中相互邻近地注入交替导电类型的多个掺杂区; 以及通过施加相同的第一和第二注入掩模来重复第一步骤和第二步骤以形成多个外延层的第三步骤，其中每个外延层被注入交替导电类型的掺杂区域。 然后通过在交变导电类型的掺杂剂区域的顶部上的外延层的顶侧上进行器件制造工艺来进行制造工艺，其具有扩散处理，以将交替导电类型的掺杂区域作为掺杂列合并在 外延层。