-
公开(公告)号:US07463533B2
公开(公告)日:2008-12-09
申请号:US11605245
申请日:2006-11-29
申请人: Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
发明人: Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
IPC分类号: G11C11/34
CPC分类号: G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
摘要翻译: 本发明的非易失性存储器件通过将针对每个编程存储单元设置的特定电容中的电荷累积并且将经过该存储单元的电荷放电时产生的热电子注入到浮动栅极中来执行编程操作。 因此,非易失性半导体存储器件的编程特性的变化减小,从而实现高速编程操作。
-
公开(公告)号:US07283400B2
公开(公告)日:2007-10-16
申请号:US11228389
申请日:2005-09-19
申请人: Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
发明人: Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
IPC分类号: G11C16/04
CPC分类号: G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
摘要翻译: 本发明的非易失性存储器件通过将针对每个编程存储单元设置的特定电容中的电荷累积并且将经过该存储单元的电荷放电时产生的热电子注入到浮动栅极中来执行编程操作。 因此,非易失性半导体存储器件的编程特性的变化减小,从而实现高速编程操作。
-
公开(公告)号:US20070076490A1
公开(公告)日:2007-04-05
申请号:US11605245
申请日:2006-11-29
申请人: Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
发明人: Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
IPC分类号: G11C16/04
CPC分类号: G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
-
公开(公告)号:US20060013032A1
公开(公告)日:2006-01-19
申请号:US11228389
申请日:2005-09-19
申请人: Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
发明人: Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase , Keiichi Yoshida , Michitaro Kanamitsu , Shoji Kubono , Atsushi Nozoe
IPC分类号: G11C17/00
CPC分类号: G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
摘要翻译: 本发明的非易失性存储器件通过将针对每个编程存储单元设置的特定电容中的电荷累积并且将经过该存储单元的电荷放电时产生的热电子注入到浮动栅极中来执行编程操作。 因此,非易失性半导体存储器件的编程特性的变化减小,从而实现高速编程操作。
-
公开(公告)号:US06950347B2
公开(公告)日:2005-09-27
申请号:US10250922
申请日:2002-01-11
申请人: Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase
发明人: Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase
CPC分类号: G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
摘要翻译: 本发明的非易失性存储器件通过将针对每个编程存储单元设置的特定电容中的电荷累积并且将经过该存储单元的电荷放电时产生的热电子注入到浮动栅极中来执行编程操作。 因此,非易失性半导体存储器件的编程特性的变化减小,从而实现高速编程操作。
-
公开(公告)号:US06459621B1
公开(公告)日:2002-10-01
申请号:US09931030
申请日:2001-08-17
申请人: Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人: Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
IPC分类号: G11C1134
CPC分类号: G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.
摘要翻译: 闪速存储器的控制包括用于向每个非易失性存储单元提供脉冲状电压的控制,直到具有第一阈值电压的非易失性存储单元的阈值电压变为第二阈值电压为止。 控制涉及第一写入模式(粗写),其中每当施加脉冲形状电压时变化的每个非易失性存储单元的阈值电压的变化量相对变高,并且第二写入 模式(高精度写入),其中阈值电压的变化量相对低。 与高精度模式相比,改变每个存储单元的阈值电压所需的脉冲数小于粗写模式时的脉冲数。 因此,使用粗写入模式时的验证操作数量很少,因此可以加快整个写入操作。
-
公开(公告)号:US06285597B1
公开(公告)日:2001-09-04
申请号:US09725011
申请日:2000-11-29
申请人: Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人: Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
IPC分类号: G11C1134
摘要: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.
-
公开(公告)号:US06496418B2
公开(公告)日:2002-12-17
申请号:US09985188
申请日:2001-11-01
申请人: Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人: Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
IPC分类号: G11C1134
CPC分类号: G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.
-
9.
公开(公告)号:US6091640A
公开(公告)日:2000-07-18
申请号:US941676
申请日:1997-09-30
申请人: Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人: Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
CPC分类号: G11C7/1045 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3459 , G11C2211/5641
摘要: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.
摘要翻译: 闪速存储器的控制包括用于向每个非易失性存储单元提供脉冲状电压的控制,直到具有第一阈值电压的非易失性存储单元的阈值电压变为第二阈值电压为止。 控制涉及第一写入模式(粗写),其中每当施加脉冲形状电压时变化的每个非易失性存储单元的阈值电压的变化量相对变高,并且第二写入 模式(高精度写入),其中阈值电压的变化量相对低。 与高精度模式相比,改变每个存储单元的阈值电压所需的脉冲数小于粗写模式时的脉冲数。 因此,使用粗写入模式时的验证操作数量很少,因此可以加快整个写入操作。
-
公开(公告)号:US6163485A
公开(公告)日:2000-12-19
申请号:US522441
申请日:2000-03-09
申请人: Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人: Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
CPC分类号: G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.
摘要翻译: 闪速存储器的控制包括用于向每个非易失性存储单元提供脉冲状电压的控制,直到具有第一阈值电压的非易失性存储单元的阈值电压变为第二阈值电压为止。 控制涉及第一写入模式(粗写),其中每当施加脉冲形状电压时变化的每个非易失性存储单元的阈值电压的变化量相对变高,并且第二写入 模式(高精度写入),其中阈值电压的变化量相对低。 与高精度模式相比,改变每个存储单元的阈值电压所需的脉冲数小于粗写模式时的脉冲数。 因此,使用粗写入模式时的验证操作数量很少,因此可以加快整个写入操作。
-
-
-
-
-
-
-
-
-