公开(公告)号：US20240243181A1

公开(公告)日：2024-07-18

申请号：US18581921

申请日：2024-02-20

Applicant: Huawei Digital Power Technologies Co., Ltd.

Inventor： Bo Gao ,  Boning Huang ,  Longgu Tang ,  Yi Zhang ,  Feng Zhou ,  Fei Hu

IPC: H01L29/423 ,  H01L21/265 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/26506 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42364 ,  H01L29/66666 ,  H01L29/7827

Abstract: A trench gate semiconductor includes a substrate having a first conductivity type; an epitaxial layer having the first conductivity type, grown on the substrate; a well region having a second conductivity type, formed on a surface layer of the epitaxial layer; a source region having the first conductivity type, formed on a surface layer of the well region; a first trench, running through the well region from a surface of the source region to the epitaxial layer; a gate, formed in the first trench in a manner of being separated by a gate insulator; and an amorphous semiconductor layer, formed in the first trench and wrapping an outer bottom wall of the gate and corners on two sides of the outer bottom wall in a manner of being separated by the gate insulator, where the amorphous semiconductor layer is made of a low dielectric constant material.

公开(公告)号：US20240297214A1

公开(公告)日：2024-09-05

申请号：US18648115

申请日：2024-04-26

Applicant: Huawei Digital Power Technologies Co., Ltd.

Inventor： Fei Hu ,  Longgu Tang ,  Yunbin Gao ,  Bo Gao

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/7813

Abstract: A semiconductor device includes an N-type semiconductor substrate, a drift layer, a semiconductor layer, a first trench located in the semiconductor layer, a gate located in the first trench, a P-well, a source region, and an N-type second semiconductor region that are located in the semiconductor layer, a source, and a drain. The drift layer includes an N-type column region and a P-type column region that are disposed in parallel and alternately. In the semiconductor device, an electrode is further disposed below the gate, a P-type first semiconductor region is disposed at the bottom of the first trench, the first semiconductor region is in contact with the electrode and the P-type column region located below the gate, and the electrode is electrically connected to the source.

公开(公告)号：US20230299155A1

公开(公告)日：2023-09-21

申请号：US18185969

申请日：2023-03-17

Applicant: Huawei Digital Power Technologies Co., Ltd.

Inventor： Longgu Tang ,  Fei Hu ,  Bo Gao ,  Chia Fu LIU ,  Boning Huang ,  Zhihua Liu

IPC: H01L29/40

CPC classification number: H01L29/402 ,  H01L29/404 ,  H01L29/0619

Abstract: A chip and an electronic device are disclosed. The chip includes a main functional area, a protection area, and a transition area located between the main functional area and the protection area. The chip includes a field oxide, a metal layer, and a passivation layer that are sequentially stacked on a semiconductor substrate. In the transition area, the field oxide includes a primary field oxide and at least one secondary field oxide that are disposed at intervals, the secondary field oxide is located on a side of the primary field oxide facing the main functional area, the metal layer extends from the main functional area to a side of the primary field oxide facing away from the semiconductor substrate. The passivation layer extends from a side of the metal layer facing away from the semiconductor substrate to a side of the metal layer facing away from the main functional area.