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1.发明申请公开(公告)号：US20220336743A1
公开(公告)日：2022-10-20
申请号：US17842800
申请日：2022-06-17
Inventor： Hao TONG , Ruizhe ZHAO , Xiangshui MIAO
IPC: H01L45/00
Abstract: The disclosure belongs to the field of microelectronics, and specifically, relates to a method of inducing crystallization of a chalcogenide phase-change material and application thereof. To be specific, a dielectric material is brought into contact with an interface of the chalcogenide phase-change material. The dielectric material is in an octahedral configuration, and the dielectric material provides a crystal nucleus growth center for the crystallization of the chalcogenide phase-change material at the interface between the two, so as to induce the phase-change material to accelerate the crystallization. The method is further applied in a phase-change memory cell. Among all the dielectric material layers in contact with the chalcogenide phase-change material layer, the dielectric material structure of at least one side of the dielectric material layer is an octahedral configuration.
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公开(公告)号：US20130270503A1
公开(公告)日：2013-10-17
申请号：US13917681
申请日：2013-06-14
Inventor： Xiangshui MIAO , Hao TONG , Xiaomin CHENG
IPC: H01L45/00
CPC classification number: H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/128 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/148 , H01L45/1608 , H01L45/1625
Abstract: A multi-layer phase change material, including: a multi-layer film structure. The multi-layer film structure includes a plurality of periodic units. The periodic units each includes a first single-layer film phase change material and a second single-layer film phase change material. The first single-layer film phase change material and the second single-layer film phase change material are alternately stacked. The first single-layer film phase change material includes chemical components that are different from chemical components included in the second single-layer film phase change material, or the first single-layer film phase change material includes chemical components that are the same as chemical components included in the second single-layer film phase change material and a percent composition of the chemical components included in the first single-layer film phase change material is different from a percent composition of the chemical components included in the second single-layer film phase change material.
Abstract translation: 一种多层相变材料，包括：多层膜结构。 多层膜结构包括多个周期性单元。 周期性单元各自包括第一单层膜相变材料和第二单层膜相变材料。 第一单层膜相变材料和第二单层膜相变材料交替堆叠。 第一单层膜相变材料包括与第二单层膜相变材料中包含的化学成分不同的化学成分，或者第一单层膜相变材料包含与化学成分相同的化学成分 包含在第二单层膜相变材料中的包含在第一单层膜相变材料中的化学成分的组成百分比与第二单层膜相变中包含的化学成分的组成百分比不同 材料。
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公开(公告)号：US20200075848A1
公开(公告)日：2020-03-05
申请号：US16679355
申请日：2019-11-11
Inventor： Xiangshui MIAO , Hao TONG , Lifan MA
Abstract: A phase-change memory cell, including, in sequence in the following order: a first electrode layer, a switching layer comprising vanadium oxide (VOx) material, a phase-change material layer, and a second electrode layer. The switching layer is adapted to control the phase-change material layer to switch between a crystalline state and an amorphous state when a voltage is applied to the first electrode layer and the second electrode layer.
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公开(公告)号：US20200052205A1
公开(公告)日：2020-02-13
申请号：US16655191
申请日：2019-10-16
Inventor： Xiangshui MIAO , Qi LIN , Hao TONG
Abstract: A selector device including a first metal electrode layer, a second metal electrode layer and a switching layer disposed between the first metal electrode layer and the second metal electrode layer. The switching layer is a stacked assembly of ABA, BAB, AB or BA, where A is an ion supply layer, and B is a conversion layer. The ion supply layer includes a chalcogenide metal material having a metal content of more than 0% and not more than 50 wt. % with respect to the chalcogenide metal material. The conversion layer includes a chalcogenide material.
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公开(公告)号：US20250113505A1
公开(公告)日：2025-04-03
申请号：US18285857
申请日：2023-05-06
Inventor： Hao TONG , Binhao WANG , Shaojie LONG , Xiangshui MIAO
Abstract: The invention discloses a three-dimensional 1S1C memory based on a ring capacitor and a preparation method. The memory includes: a horizontal peripheral electrode layer including a first dielectric layer and a first metal electrode layer alternately stacked and grown on a substrate and provided with trenches penetrating in a vertical direction and holes penetrating in the vertical direction, a vertical functional layer, and a capacitive dielectric layer. An annular groove is disposed outside each hole. The annular groove surrounds the holes and vertically cuts off the peripheral electrode layer. The annular groove is evenly filled with a capacitive dielectric layer. A top of the second metal electrode layer is extended to a surface of a topmost first dielectric layer to form a bit line electrode and is connected to a bit line. A region where the second metal electrode layer faces the first metal electrode layer forms a memory cell.
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Patent Agency Ranking
公开(公告)号：US20210043255A1
公开(公告)日：2021-02-11
申请号：US17037655
申请日：2020-09-29
Inventor： Xiangshui MIAO , Qi LIN , Hao TONG
IPC: G11C13/00
Abstract: An operating method for improving the performance of a selector device is provided, including: determining and applying a direct current (DC) or alternating current (AC) operating voltage and a limit current of the selector device, so that the selector device circulates until a off-state resistance is reduced; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is reduced to a minimum value; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is increased; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is increased to a maximum value; and adjusting the operating voltage and the limit current, and performing DC or AC operation pulsed operation on a selector.
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公开(公告)号：US20230165171A1
公开(公告)日：2023-05-25
申请号：US17767927
申请日：2021-12-01
Inventor： Hao TONG , Lun WANG , Weiguo WANG , Xiangshui MIAO
CPC classification number: H10N70/231 , H10N70/8845 , H10N70/841 , H10N70/026 , H10N70/023 , H10B63/80 , H10N70/882
Abstract: A selector with a superlattice-like structure and a preparation method thereof are provided, which belong to the technical field of micro-nano electronics. The selector includes a substrate, and a first metal electrode layer, a superlattice-like layer, and a second metal electrode layer sequentially stacked on the substrate. The superlattice-like layer includes n+1 first sublayers and n second sublayers alternately stacked periodically. A material of the first sublayer is amorphous carbon, and a material of the second sublayer is a chalcogenide with gating property.
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公开(公告)号：US20220351026A1
公开(公告)日：2022-11-03
申请号：US17259191
申请日：2020-05-28
Inventor： Hao TONG , Qing HU , Yuhui HE , Xiangshui MIAO
Abstract: The disclosure discloses a three-dimensional (3D) convolution operation device and method based on a 3D phase change memory, which includes a 3D phase change memory, an input control module, a setting module, and an output control module. By using the 3D phase change memory to perform 3D convolution operation, the phase change units on the same bit line constitute a convolution kernel. Based on the multilayer stack structure, the upper and lower electrodes of the 3D phase change memory serve as the information input terminal, and they are convolved after passing through the respective phase change unit arrays, and the result of the convolution operation is superposed on the middle electrode in the form of current, thereby obtaining the sum of the convolution calculation results of the input information of the upper and lower electrodes, such that the 3D convolution operation is completed in one step.
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公开(公告)号：US20210104670A1
公开(公告)日：2021-04-08
申请号：US17040998
申请日：2018-08-09
Inventor： Xiangshui MIAO , Hao TONG , Yushan SHEN
Abstract: The disclosure discloses a three-dimensional stacked memory and a preparation method thereof. The storage unit adopts a constrained structure phase change storage unit, and uses a crossbar storage array structure to build a large-capacity storage array. The preparation method includes: preparing N first strip-shaped electrodes along a crystal direction on a substrate; preparing a first insulating layer with M*N array of through holes; filling the M*N array of through holes of the first insulating layer with a phase change material to form first phase change units; preparing M second strip-shaped electrodes; preparing a second insulating layer, using spin-coated photoresist as a sacrificial material, performing a local planarization on the surface of the second insulating layer; forming M*N array of through holes on the second insulating layer; filling a phase change material to form second phase change units; preparing N third strip-shaped electrodes to form a two-layer stacked phase change memory.
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公开(公告)号：US20240379159A1
公开(公告)日：2024-11-14
申请号：US18033075
申请日：2022-01-25
Inventor： Hao TONG , Binhao Wang , Xiangshui MIAO
IPC: G11C13/00
Abstract: Disclosed are an OTS-based dynamic storage structure and an operation method thereof. The OTS-based dynamic storage structure includes a plurality of storage units distributed in an array, and each storage unit includes an OTS gating transistor and a storage capacitor. The OTS gating transistor has two states, namely, high resistance state and low resistance state. When the voltage across the OTS gating transistor exceeds the threshold voltage Vth, the OTS gating transistor is switched from the high resistance state to the low resistance state. When the voltage across the OTS gating transistor in the low resistance state is lower than the holding voltage Vhold, the OTS gating transistor is switched from the low resistance state to the high resistance state.
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