公开(公告)号：US20110284937A1

公开(公告)日：2011-11-24

申请号：US12858702

申请日：2010-08-18

申请人： Hyung Jun KIM ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

发明人： Hyung Jun KIM ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

IPC分类号： H01L29/82

CPC分类号： H01L29/66984 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  Y10S257/902

摘要： A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.

摘要翻译： 一种自旋晶体管，包括：包括上包层和下包层的半导体衬底，以及介于上包层和下包层之间的沟道层; 形成在所述半导体基板上并且在所述沟道层的长度方向上彼此间隔开的铁磁源和铁磁性漏极; 以及形成在所述源极和漏极之间的所述半导体衬底上并且施加了栅极电压以用于控制通过所述沟道层的电子的自旋进动的栅电极，其中所述半导体衬底包括具有第一导电性的第一载流子供应层 类型，其设置在所述下包层下方并且将沟道层供给到所述沟道层;以及第二导电类型的第二载流子供应层，其形成在所述上包层上并且将所述载流子提供给所述沟道层。

公开(公告)号：US08183611B2

公开(公告)日：2012-05-22

申请号：US12858702

申请日：2010-08-18

申请人： Hyung Jun Kim ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

发明人： Hyung Jun Kim ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

IPC分类号： H01L29/76

CPC分类号： H01L29/66984 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  Y10S257/902

摘要： A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.

摘要翻译： 一种自旋晶体管，包括：包括上包层和下包层的半导体衬底，以及介于上包层和下包层之间的沟道层; 形成在所述半导体基板上并且在所述沟道层的长度方向上彼此间隔开的铁磁源和铁磁性漏极; 以及形成在所述源极和漏极之间的所述半导体衬底上并且施加了栅极电压以用于控制通过所述沟道层的电子的自旋进动的栅电极，其中所述半导体衬底包括具有第一导电性的第一载流子供应层 类型，其设置在所述下包层下方并且将沟道层供给到所述沟道层;以及第二导电类型的第二载流子供应层，其形成在所述上包层上并且将所述载流子提供给所述沟道层。

公开(公告)号：US08586964B2

公开(公告)日：2013-11-19

申请号：US12911560

申请日：2010-10-25

申请人： Jin-Dong Song ,  Sang Hoon Shin ,  Hyung-jun Kim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Joonyeon Chang

发明人： Jin-Dong Song ,  Sang Hoon Shin ,  Hyung-jun Kim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Joonyeon Chang

IPC分类号： H01L29/15

CPC分类号： H01L29/7783 ,  B82Y10/00 ,  H01L29/122

摘要： Disclosed herein are a method of generating a two-dimensional hole gas (2DHG) using a type-2 quantum well formed using semiconductors with different electron affinities or band gap, and a high-speed p-type semiconductor device using the 2DHG. To this end, the method includes providing a semiconductor substrate; growing a first semiconductor layer on the semiconductor substrate, growing a second semiconductor layer with a different electron affinity or band gap from the first semiconductor layer on the first semiconductor layer, and growing a third semiconductor layer with a different electron affinity or band gap from the second semiconductor layer, thereby forming a type-2 quantum well; and forming a p-type doping layer in the vicinity of the type-2 quantum well, thereby generating the 2DHG.

摘要翻译： 本文公开了使用具有不同电子亲和性或带隙的半导体形成的2型量子阱和使用该2DHG的高速p型半导体器件来生成二维空穴气体（2DHG）的方法。 为此，该方法包括提供半导体衬底; 在所述半导体衬底上生长第一半导体层，在所述第一半导体层上生长具有与所述第一半导体层不同的电子亲和性或带隙的第二半导体层，以及生长具有与所述第一半导体层不同的电子亲和性或带隙的第三半导体层 第二半导体层，从而形成2型量子阱; 并在2型量子阱附近形成p型掺杂层，从而生成2DHG。

公开(公告)号：US20120007045A1

公开(公告)日：2012-01-12

申请号：US12911560

申请日：2010-10-25

申请人： JIN-DONG SONG ,  Sang Hoon Shin ,  Hyung-jun Kim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Joonyeon Chang

发明人： JIN-DONG SONG ,  Sang Hoon Shin ,  Hyung-jun Kim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Joonyeon Chang

IPC分类号： H01L29/15 ,  H01L21/20

CPC分类号： H01L29/7783 ,  B82Y10/00 ,  H01L29/122

摘要： Disclosed herein are a method of generating a two-dimensional hole gas (2DHG) using a type-2 quantum well formed using semiconductors with different electron affinities or band gap, and a high-speed p-type semiconductor device using the 2DHG. To this end, the method includes providing a semiconductor substrate; growing a first semiconductor layer on the semiconductor substrate, growing a second semiconductor layer with a different electron affinity or band gap from the first semiconductor layer on the first semiconductor layer, and growing a third semiconductor layer with a different electron affinity or band gap from the second semiconductor layer, thereby forming a type-2 quantum well; and forming a p-type doping layer in the vicinity of the type-2 quantum well, thereby generating the 2DHG.

摘要翻译： 本文公开了使用具有不同电子亲和性或带隙的半导体形成的2型量子阱和使用该2DHG的高速p型半导体器件来生成二维空穴气体（2DHG）的方法。 为此，该方法包括提供半导体衬底; 在所述半导体衬底上生长第一半导体层，在所述第一半导体层上生长具有与所述第一半导体层不同的电子亲和性或带隙的第二半导体层，以及生长具有与所述第一半导体层不同的电子亲和性或带隙的第三半导体层 第二半导体层，从而形成2型量子阱; 并在2型量子阱附近形成p型掺杂层，从而生成2DHG。

公开(公告)号：US08058676B2

公开(公告)日：2011-11-15

申请号：US12342426

申请日：2008-12-23

申请人： Hyung Jun Kim ,  Hyun Cheol Koo ,  Joon Yeon Chang ,  Suk Hee Han ,  Kyung Ho Kim

发明人： Hyung Jun Kim ,  Hyun Cheol Koo ,  Joon Yeon Chang ,  Suk Hee Han ,  Kyung Ho Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/66984 ,  H01L29/7785

摘要： A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer.

摘要翻译： 自旋晶体管包括：半导体衬底，包括具有二维电子气体结构的沟道层和分别设置在沟道层的上侧和下侧的上和下包层; 形成在所述半导体衬底上并且彼此间隔开的铁磁源极和漏极; 栅电极，设置在源电极和漏电极之间并且施加栅极电压以控制通过沟道层的电子的自旋; 第一载流子供给层，设置在所述下包层和所述沟道层之间，以向所述沟道层提供载流子; 以及第二载体供给层，其设置在所述上​​包层和所述沟道层之间，以将载流子供应到所述沟道层。

公开(公告)号：US20100084633A1

公开(公告)日：2010-04-08

申请号：US12342426

申请日：2008-12-23

申请人： Hyung Jun Kim ,  Hyun Cheol Koo ,  Joon Yeon Chang ,  Suk Hee Han ,  Kyung Ho Kim

发明人： Hyung Jun Kim ,  Hyun Cheol Koo ,  Joon Yeon Chang ,  Suk Hee Han ,  Kyung Ho Kim

IPC分类号： H01L29/66

CPC分类号： H01L29/66984 ,  H01L29/7785

摘要： A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer.

摘要翻译： 自旋晶体管包括：半导体衬底，包括具有二维电子气体结构的沟道层和分别设置在沟道层的上侧和下侧的上和下包层; 形成在所述半导体衬底上并且彼此间隔开的铁磁源极和漏极; 栅电极，设置在源电极和漏电极之间并且施加栅极电压以控制通过沟道层的电子的自旋; 第一载流子供给层，设置在所述下包层和所述沟道层之间，以向所述沟道层提供载流子; 以及第二载体供给层，其设置在所述上​​包层和所述沟道层之间，以将载流子供应到所述沟道层。

公开(公告)号：US08053851B2

公开(公告)日：2011-11-08

申请号：US12233488

申请日：2008-09-18

申请人： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Kyung Ho Kim

发明人： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Kyung Ho Kim

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L29/205 ,  B82Y10/00 ,  H01L29/122 ,  H01L29/66984 ,  Y10S977/933

摘要： A spin transistor conducive to the miniaturization and large scale integration of devices, because a magnetization direction of a source and a drain is determined by a direction of the epitaxial growth of a ferromagnet. The spin transistor includes a semiconductor substrate having a channel layer formed thereinside; ferromagnetic source and drain epitaxially grown on the semiconductor substrate and magnetized in a longitudinal direction of the channel layer due to magnetocrystalline anisotropy—the source and drain being disposed spaced apart from each other in a channel direction and magnetized in the same direction—; and a gate disposed between the source and the drain to be insulated with the semiconductor substrate and formed on the semiconductor substrate to control the spin of electrons that are passed through the channel layer.

摘要翻译： 有助于器件的小型化和大规模集成的自旋晶体管，因为源极和漏极的磁化方向由铁磁体的外延生长的方向决定。 自旋晶体管包括其内部形成有沟道层的半导体衬底; 外延生长在半导体衬底上的铁磁源极和漏极，并且由于磁晶各向异性而在沟道层的纵向上被磁化 - 源极和漏极沿沟道方向彼此间隔开并沿相同方向被磁化; 以及设置在源极和漏极之间的栅极，与半导体衬底绝缘并形成在半导体衬底上，以控制通过沟道层的电子的自旋。

公开(公告)号：US08775139B2

公开(公告)日：2014-07-08

申请号：US13162406

申请日：2011-06-16

申请人： Jae Wan Shim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Byoung Chul Min ,  Jun Woo Choi ,  Kyung Ho Shin ,  Jin Dong Song

发明人： Jae Wan Shim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Byoung Chul Min ,  Jun Woo Choi ,  Kyung Ho Shin ,  Jin Dong Song

IPC分类号： G06G7/50 ,  G06G7/48 ,  G06F17/50 ,  G06T13/20 ,  G06T13/80

CPC分类号： G06F17/5018 ,  G06F17/5009 ,  G06F2217/16 ,  G06T13/20 ,  G06T13/80

摘要： A method for simulating fluid flow includes: discretizing a space in which a fluid flows into a regular lattice; assuming that fluid particles repetitively move and collide in the lattice; deriving a univariate polynomial equation by comparing the n-th (n is a non-negative integer) order momentum of velocity between the Maxwell-Boltzmann distribution and the discretized Maxwell-Boltzmann distribution; calculating the weight coefficients corresponding to the discrete velocities of the fluid particles based on the univariate polynomial equation; and deriving a lattice Boltzmann model using the weight coefficients. A lattice Boltzmann model with superior stability and accuracy may be derived easily.

摘要翻译： 用于模拟流体流动的方法包括：离散流体流入规则晶格的空间; 假设流体颗粒在格子中重复地移动和碰撞; 通过比较Maxwell-Boltzmann分布与离散Maxwell-Boltzmann分布之间的速度的第n（n是非负整数）阶次动量，得出单变量多项式方程; 基于单变量多项式方程计算与流体颗粒的离散速度对应的权重系数; 并使用权重系数导出格子波尔兹曼模型。 可以很容易地得出具有优异的稳定性和精度的晶格玻尔兹曼模型。

公开(公告)号：US20110279146A1

公开(公告)日：2011-11-17

申请号：US12899778

申请日：2010-10-07

申请人： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jun Woo Choi

发明人： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jun Woo Choi

IPC分类号： H03K19/091

CPC分类号： H03K19/091 ,  B82Y10/00 ,  G11C11/16 ,  H03K19/18

摘要： There is provided a complementary spin transistor logic circuit, including: a parallel spin transistor that includes a magnetized first source, a first drain magnetized in parallel with the magnetization direction of the first source, a first channel layer and a first gate electrode; and an anti-parallel spin transistor that includes a magnetized second source, a second drain magnetized in anti-parallel with the magnetization direction of the second source, a second channel layer and a second gate electrode, wherein the first gate electrode and the second gate electrode are connected to a common input terminal.

摘要翻译： 提供了一种互补自旋晶体管逻辑电路，包括：并联自旋晶体管，其包括磁化的第一源，与第一源的磁化方向平行磁化的第一漏极，第一沟道层和第一栅电极; 以及反并联自旋晶体管，其包括磁化的第二源极，与所述第二源极的磁化方向反并联的第二漏极，第二沟道层和第二栅电极，其中所述第一栅电极和所述第二栅极 电极连接到公共输入端子。

公开(公告)号：US20110042648A1

公开(公告)日：2011-02-24

申请号：US12684586

申请日：2010-01-08

申请人： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jang Hae Ku

发明人： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jang Hae Ku

IPC分类号： H01L29/82 ,  H01L29/66

CPC分类号： H01L29/66984 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/7783

摘要： A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.

摘要翻译： 逻辑器件包括：具有沟道层的衬底; 铁磁材料的两个输入端子图案形成在基板上并且沿着沟道层的纵向方向彼此间隔开，以便用作逻辑门的输入端; 以及形成在所述基板上并且设置在所述两个输入端子图案之间以用作所述逻辑门的输出端子的铁磁材料的输出端子图案。 输出端子图案通过使用从输入端子图案注入到沟道层中的电子自旋的自旋累积和扩散来读取输出电压。