公开(公告)号：US20230200263A1

公开(公告)日：2023-06-22

申请号：US18060389

申请日：2022-11-30

Applicant: IMEC VZW

Inventor： Jaber Derakhshandeh ,  Iuliana Radu ,  Eric Beyne ,  Bogdan Govoreanu

IPC: H10N69/00 ,  H01L23/00 ,  H01L23/538

CPC classification number: H10N69/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/05 ,  H01L24/08 ,  H01L23/5384 ,  H01L24/14 ,  H01L24/06 ,  H01L2224/13109 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/05609 ,  H01L2224/08225 ,  H01L2224/0557 ,  H01L2224/06181

Abstract: The present disclosure relates to a quantum bit (qubit) chip. The qubit chip includes two or more qubit wafers arranged along a common axis and one or more spacer elements. The spacer elements and the qubit wafers are alternately arranged on the common axis. The qubit chip further includes a conductive arrangement configured to electrically connect the two or more qubit wafers, where the conductive arrangement includes at least one superconducting via per each qubit wafer of the two or more qubit wafers and each spacer element of the one or more spacer elements, the at least one superconducting via passing through the qubit wafer or spacer element.

公开(公告)号：US20130187680A1

公开(公告)日：2013-07-25

申请号：US13744625

申请日：2013-01-18

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, K.U. LEUVEN R&D

Inventor： Koen Martens ,  Iuliana Radu

IPC: H03K19/20

CPC classification number: H03K19/20

Abstract: A complementary logic technology is disclosed whereby a logic gate comprises at least two metal-to-insulator transition (MIT) elements and at least two thermoelectric elements, each MIT element being thermally coupled to a corresponding thermoelectric element. In logic gates, each electric signal at an input terminal of a logic gate is first converted into two complementary thermal signals, and these thermal signals in turn determine the status of the output terminal of the logic gate, thereby generating an electrical output signal inverse to the electrical input signal or an output signal which is a Boolean operation on input signals. The parallel connection(s) of thermoelectric elements of the logic gate is used to create corresponding thermal signals for each electrical input signal. The MIT elements of the logic gate are then arranged to, in response to the associated thermal signals, execute a Boolean operation.

Abstract translation: 公开了一种互补逻辑技术，由此逻辑门包括至少两个金属至绝缘体转变（MIT）元件和至少两个热电元件，每个MIT元件热耦合到相应的热电元件。 在逻辑门中，逻辑门的输入端的每个电信号首先转换成两个互补的热信号，这些热信号又决定了逻辑门的输出端的状态，从而产生与 电输入信号或对输入信号进行布尔运算的输出信号。 逻辑门的热电元件的并联连接用于为每个电输入信号产生相应的热信号。 然后逻辑门的MIT元件被布置为响应于相关联的热信号执行布尔运算。

公开(公告)号：US20230189497A1

公开(公告)日：2023-06-15

申请号：US18064133

申请日：2022-12-09

Applicant: IMEC VZW

Inventor： Cedric Huyghebaert ,  Tom Schram ,  Iuliana Radu

IPC: H10B10/00 ,  G11C11/419

CPC classification number: H10B10/125 ,  G11C11/419

Abstract: The present disclosure relates generally to static random-access memory (SRAM) devices. Specifically, the disclosure proposes a SRAM device with a three-layered SRAM cell design. The SRAM cell comprises a storage comprising four storage transistors, and comprises two access transistors to control access to the storage cell. The SRAM cell further comprises a stack of three layer structures. Two of the storage transistors are formed in a first layer structure of the stack, and two other of the storage transistors are formed in a second layer structure of the stack adjacent to the first layer structure. The two access transistors are formed in a third layer structure of the stack adjacent to the second layer structure. Each layer structure comprises a semiconductor material, the transistors in the layer structure are based on that semiconductor material, and at least two of the three layer structures comprise a different type of semiconductor material.

公开(公告)号：US09979402B2

公开(公告)日：2018-05-22

申请号：US15586165

申请日：2017-05-03

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Adrien Vaysset ,  Iuliana Radu ,  Geoffrey Pourtois

IPC: H03K19/23 ,  H03K19/18 ,  H01L43/08

CPC classification number: H03K19/23 ,  H01L43/08 ,  H03K19/18

Abstract: The disclosed technology generally relates to magnetic devices and more particularly to spin torque majority gate devices, and to methods of operating such devices. In one aspect, a majority gate device comprises a free ferromagnetic layer comprising 3N input zones and an output zone. The output zone has a polygon shape having 3N sides, where each input zone adjoins the output zone. The input zones are arranged around the output zone according to a 3N-fold rotational symmetry, where N is a positive integer greater than 0. The input zones are spaced apart from one another by the output zone. The majority gate device additionally comprises a plurality of input controls, where each of the input zones is magnetically coupled to a corresponding one of the plurality of input controls, where each of the input controls is configured to control the magnetization state of the corresponding input zone. The majority gate device further comprises an output sensor magnetically coupled to the output zone, where the output sensor is adapted for sensing the magnetization state of the output zone. Each input zones adjoins the output zone at one of the 3N sides.