公开(公告)号：US10903335B2

公开(公告)日：2021-01-26

申请号：US16408971

申请日：2019-05-10

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Sylvain Baudot ,  Hans Mertens ,  Julien Jussot

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423

Abstract: A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.

公开(公告)号：US20210391526A1

公开(公告)日：2021-12-16

申请号：US17345827

申请日：2021-06-11

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Ruoyu Li ,  Stefan Kubicek ,  Julien Jussot

IPC: H01L39/24 ,  H01L27/18 ,  H01L39/08 ,  H01L39/22

Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

公开(公告)号：US20240204066A1

公开(公告)日：2024-06-20

申请号：US18543315

申请日：2023-12-18

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Julien Jussot

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H01L29/41758 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696 ,  H10B10/12

Abstract: The disclosure relates to a semiconductor device structure. The device structure comprises a first and second FETs, each comprising respective S/D structures, a respective channel structure and a respective gate structure. Each S/D structure comprises an S/D body and a set of vertically spaced apart S/D prongs protruding laterally from the S/D body. The S/D prongs of the first and second FETs extend in opposite lateral directions. Each gate structure comprises a gate body and a set of gate prongs protruding laterally from the gate body into spaces between channel layers of the respective channel structures. The gate prongs of the first and second FETs extend in opposite lateral directions.

公开(公告)号：US11638391B2

公开(公告)日：2023-04-25

申请号：US17345827

申请日：2021-06-11

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Ruoyu Li ,  Stefan Kubicek ,  Julien Jussot

IPC: H10N60/01 ,  H10N60/10 ,  H10N60/83 ,  H10N69/00

Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

公开(公告)号：US11114337B2

公开(公告)日：2021-09-07

申请号：US16716025

申请日：2019-12-16

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Julien Jussot ,  Geert Van der Plas

IPC: H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A method is provided for bonding and interconnecting two semiconductor chips arranged on semiconductor substrates. HSQ (Hydrogen Silsesquioxane) or an equivalent material is used as a bonding layer and after bonding and thinning one of the wafers (or first thinning and then bonding), the bond layer is locally irradiated by an e-beam through the thinned substrate, thereby locally transforming the bonding material into silicon oxide. Then a via opening is etched through the thinned substrate and an etch process selectively removes the oxide from an area delimited by the bonding material or vice versa. The filling of the via opening establishes an electrical connection between the bonded wafers, that is equivalent to a connection obtained by hybrid bonding, but that does not suffer from the disadvantages thereof.