公开(公告)号：US20210074830A1

公开(公告)日：2021-03-11

申请号：US17013230

申请日：2020-09-04

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Sylvain Baudot

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method for electrically isolating a vertical nanowire on at least one location in the nanowire. The method comprises providing a substrate, forming a vertical nanowire stack on the substrate. The stack comprises at least one nanowire section of a first material. A sacrificial section of a second material is provided in the vertical nanowire stack on the at least one location. The second material is selected such that it can be selectively removed with respect to the first material. The method, moreover, comprises creating at least one interconnect to the at least one nanowire section which should be isolated, removing the at least one sacrificial section and replacing it with an isolating section after creating the interconnect.

公开(公告)号：US10903335B2

公开(公告)日：2021-01-26

申请号：US16408971

申请日：2019-05-10

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Sylvain Baudot ,  Hans Mertens ,  Julien Jussot

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423

Abstract: A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.

公开(公告)号：US10998413B2

公开(公告)日：2021-05-04

申请号：US16711258

申请日：2019-12-11

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Sylvain Baudot ,  Geert Van der Plas

IPC: H01L21/8234 ,  H01L29/45 ,  H01L21/762 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

Abstract: The disclosed technology relates generally to integrated circuit structures, and more particularly to a semiconductor fin structure having silicided portions. In an aspect, a semiconductor device including a fin structure and a substrate is disclosed. The fin structure includes a first source/drain region, a second source/drain region, and a channel region. The channel region is arranged between the first source/drain region and the second source/drain region to separate the first source/drain region and the second source/drain region in a length direction of the fin structure. The first source/drain region includes a bottom portion and a top portion, wherein the bottom portion of the first source/drain region is fully silicided and the top portion of the first source/drain region is partly silicided.

公开(公告)号：US20240170559A1

公开(公告)日：2024-05-23

申请号：US18507928

申请日：2023-11-13

Applicant: IMEC VZW

Inventor： Sylvain Baudot ,  Stefan Kubicek ,  Shana Massar

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/51

CPC classification number: H01L29/66977 ,  H01L29/401 ,  H01L29/511 ,  H01L29/6656

Abstract: A method for producing a plurality of mutually parallel mandrel structures of a quantum dot device is provided. The method includes producing mutually parallel mandrel structures on a substrate including at least a top layer of semiconductor material. Side spacers are formed on the mandrel structures, and the mandrel structures are removed with respect to the spacers. The gate oxide of a quantum dot device can be formed in the areas between the spacers, by a thermal oxidation of the semiconductor material of the substrate. The thermal oxidation enables the formation of a gate oxide having low defect density and a constant thickness. The spacer material can be chosen to withstand the thermal oxidation and acts as an insulator between the gate structures.

公开(公告)号：US20210134995A1

公开(公告)日：2021-05-06

申请号：US17090758

申请日：2020-11-05

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Sylvain Baudot

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to a vertical channel device and a method of forming a vertical channel device. In one aspect, a method of forming a vertical channel transistor structure comprises the steps of: (a) forming a bottom source/drain region on a substrate surface and depositing a spacer oxide layer over the bottom source/drain region; (b) forming vertically extending portions and depositing a gate material on the deposited spacer oxide layer such that the gate material is arranged over the bottom source/drain region and over the deposited spacer oxide layer, wherein the vertically extending portions are arranged around and extend above the gate material; and (c) depositing a spacer material at sidewalls of the vertically extending portions, thereby defining a horizontal gap between the vertically extending portions, the gap being positioned vertically over the gate material and the bottom source/drain portion. The method further comprises the steps of: (d) forming a vertical opening through the gate material extending from the horizontal gap down to the bottom source/drain region; (e) depositing an oxide at sidewalls of the gate material in the vertical opening; (f) performing an epitaxial deposition process of a semiconductor material on the bottom source/drain portion to form a vertical channel structure above the gate material, wherein a width (w1) of the vertical channel structure through the gate is defined by a width of the horizontal gap after depositing the oxide in step (e); (g) planarizing the vertical channel transistor structure, thereby reducing the height of the vertical channel structure and the spacer material; and (h) forming a top source/drain region over the vertical channel structure.