Control and readout topology for spin qubits

    公开(公告)号:US12204996B2

    公开(公告)日:2025-01-21

    申请号:US17645209

    申请日:2021-12-20

    Applicant: IMEC vzw

    Abstract: An integrated system for quantum computation is provided, In one aspect, the system includes at least one semiconductor spin quantum bit (qubit); a feedline configured to act as an electron spin resonance (ESR) antenna for control of the at least one qubit; at least one resonator; and a ground plane common to both the feedline and the at least one resonator. The at least one resonator is capacitively coupled to the feedline, and configured for readout of the at least one qubit via the feedline. The feedline and the at least one resonator are arranged in adjacent layers separated by at least a dielectric. A corresponding method of performing quantum computation using such an integrated system is also provided.

    Qubit Device
    2.
    发明公开
    Qubit Device 审中-公开

    公开(公告)号:US20230196166A1

    公开(公告)日:2023-06-22

    申请号:US18060154

    申请日:2022-11-30

    Applicant: IMEC VZW

    CPC classification number: G06N10/40 G06N10/20 H10N69/00

    Abstract: A qubit device includes first and second linear qubit arrays. Each qubit array includes a semiconductor substrate, control gates configured to define a single row of quantum dots along the substrate, and nanomagnets distributed along the row of quantum dots such that a nanomagnet is arranged at every other pair of quantum dots of the row of quantum dots. Each nanomagnet has an out-of-plane magnetization with respect to the substrate, where the rows of the first and second arrays extend in a common row direction and are separated along a direction transverse to the row direction. The qubit device further includes superconducting resonators connecting pairs of quantum dots between the first and second arrays. Each pair of quantum dots in the first array is configured to couple with a superconducting resonator of the first set to connect with a different pair of quantum dots of the second array.

    Method for processing a semiconductor device with two closely spaced gates

    公开(公告)号:US11638391B2

    公开(公告)日:2023-04-25

    申请号:US17345827

    申请日:2021-06-11

    Applicant: IMEC VZW

    Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

    METHOD FOR PROCESSING A SEMICONDUCTOR DEVICE WITH TWO CLOSELY SPACED GATES

    公开(公告)号:US20210391526A1

    公开(公告)日:2021-12-16

    申请号:US17345827

    申请日:2021-06-11

    Applicant: IMEC VZW

    Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

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