METHOD FOR PROCESSING A SEMICONDUCTOR DEVICE WITH TWO CLOSELY SPACED GATES

    公开(公告)号:US20210391526A1

    公开(公告)日:2021-12-16

    申请号:US17345827

    申请日:2021-06-11

    Applicant: IMEC VZW

    Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

    METHOD FOR PRODUCING CLOSELY SPACED GATE STRUCTURES OF A QUANTUM DOT DEVICE

    公开(公告)号:US20240170559A1

    公开(公告)日:2024-05-23

    申请号:US18507928

    申请日:2023-11-13

    Applicant: IMEC VZW

    CPC classification number: H01L29/66977 H01L29/401 H01L29/511 H01L29/6656

    Abstract: A method for producing a plurality of mutually parallel mandrel structures of a quantum dot device is provided. The method includes producing mutually parallel mandrel structures on a substrate including at least a top layer of semiconductor material. Side spacers are formed on the mandrel structures, and the mandrel structures are removed with respect to the spacers. The gate oxide of a quantum dot device can be formed in the areas between the spacers, by a thermal oxidation of the semiconductor material of the substrate. The thermal oxidation enables the formation of a gate oxide having low defect density and a constant thickness. The spacer material can be chosen to withstand the thermal oxidation and acts as an insulator between the gate structures.

    Qubit Device
    4.
    发明公开
    Qubit Device 审中-公开

    公开(公告)号:US20230196166A1

    公开(公告)日:2023-06-22

    申请号:US18060154

    申请日:2022-11-30

    Applicant: IMEC VZW

    CPC classification number: G06N10/40 G06N10/20 H10N69/00

    Abstract: A qubit device includes first and second linear qubit arrays. Each qubit array includes a semiconductor substrate, control gates configured to define a single row of quantum dots along the substrate, and nanomagnets distributed along the row of quantum dots such that a nanomagnet is arranged at every other pair of quantum dots of the row of quantum dots. Each nanomagnet has an out-of-plane magnetization with respect to the substrate, where the rows of the first and second arrays extend in a common row direction and are separated along a direction transverse to the row direction. The qubit device further includes superconducting resonators connecting pairs of quantum dots between the first and second arrays. Each pair of quantum dots in the first array is configured to couple with a superconducting resonator of the first set to connect with a different pair of quantum dots of the second array.

    Method for processing a semiconductor device with two closely spaced gates

    公开(公告)号:US11638391B2

    公开(公告)日:2023-04-25

    申请号:US17345827

    申请日:2021-06-11

    Applicant: IMEC VZW

    Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

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