公开(公告)号：US11776564B2

公开(公告)日：2023-10-03

申请号：US17645663

申请日：2021-12-22

Applicant: IMEC vzw

Inventor： Maarten Rosmeulen ,  Arnaud Furnemont ,  Devin Verreck ,  Antonio Arreghini ,  Willem Van Roy ,  Kherim Willems

IPC: G11B3/00

CPC classification number: G11B3/008

Abstract: A memory device including at least one channel and a fluid including particles is provided. In one aspect, the channel includes a least some of the fluid. The memory device may further include an actuator configured to induce a movement of the particles in the channel; and a writing element configured to arrange the particles in a sequence, thereby yielding a sequence of particles in the channel. The particles may include first particles and second particles. The particles may be in a first state or a second state in the channel. In certain aspects, the channel is configured to preserve the sequence of the particles. The memory device may further include a reading element for detecting the sequence of the particles in the channel.

公开(公告)号：US20190198525A1

公开(公告)日：2019-06-27

申请号：US16218271

申请日：2018-12-12

Applicant: IMEC vzw

Inventor： Antonio Arreghini

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/1159 ,  H01L27/11597

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7889 ,  H01L29/7926

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to three-dimensional semiconductor devices. In one aspect, a method of manufacturing a three-dimensional (3D) semiconductor device includes providing a horizontal layer structure above a substrate and forming an opening that extends vertically through the horizontal layer structure to the substrate. The method additionally includes lining an inside vertical surface of the opening with a gate stack and lining the inside vertical surface of the opening having the gate stack formed thereon with a sacrificial material layer. The method additionally includes filling the opening with a filling material and removing the sacrificial material layer to form a recess. The method further includes forming the channel by epitaxially growing, in the recess, a channel material upwards from the substrate.

公开(公告)号：US11387248B2

公开(公告)日：2022-07-12

申请号：US16218271

申请日：2018-12-12

Applicant: IMEC vzw

Inventor： Antonio Arreghini

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/786 ,  H01L29/792 ,  H01L21/768 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/11524 ,  H01L27/1157

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to three-dimensional semiconductor devices. In one aspect, a method of manufacturing a three-dimensional (3D) semiconductor device includes providing a horizontal layer structure above a substrate and forming an opening that extends vertically through the horizontal layer structure to the substrate. The method additionally includes lining an inside vertical surface of the opening with a gate stack and lining the inside vertical surface of the opening having the gate stack formed thereon with a sacrificial material layer. The method additionally includes filling the opening with a filling material and removing the sacrificial material layer to form a recess. The method further includes forming the channel by epitaxially growing, in the recess, a channel material upwards from the substrate.

公开(公告)号：US11107529B2

公开(公告)日：2021-08-31

申请号：US16365504

申请日：2019-03-26

Applicant: IMEC vzw

Inventor： Antonio Arreghini ,  Arnaud Furnemont

IPC: G11C13/02 ,  G11C11/22 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/788 ,  G11C13/00 ,  G11C16/06 ,  C25B9/17

Abstract: The disclosed technology relates to a molecular synthesis device. In one aspect, the molecular synthesis device comprises a synthesis array having an array of synthesis locations and an electrode arranged at each synthesis locations. The molecular synthesis device further comprises a non-volatile memory having an array of bit cells and a set of wordlines and a set of bitlines. Each bit cell comprises a non-volatile memory transistor having a control gate connected to a wordline, a first source/drain terminal, and a second source/drain terminal connected to a bitline. The electrode at each synthesis locations of the synthesis array is connected to the first source/drain terminal of a corresponding bit cell of the non-volatile memory.