公开(公告)号：US20160104769A1

公开(公告)日：2016-04-14

申请号：US14880667

申请日：2015-10-12

Applicant: IMEC VZW

Inventor： Devin Verreck ,  Anne S. Verhulst

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/0688 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/365 ,  H01L29/42356 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78

Abstract: A p-type Tunnel Field-Effect Transistor comprises a drain p-type semiconductor region, a source n-type semiconductor region, and at least one gate stack. The source n-type semiconductor region comprises a lowly doped section with a length of at least 10 nm and with a doping level of n-type dopant elements below 5×1018 at/cm3 and, in contact with the lowly doped section, a highly doped section with a length between 1 monolayer and 20 nm and with a doping level of n-type dopant elements above 5×1018 at/cm3.

Abstract translation: p型隧道场效应晶体管包括漏极p型半导体区域，源极n型半导体区域和至少一个栅极叠层。 源极n型半导体区域包括长度至少为10nm的低掺杂部分，并且n型掺杂元素的掺杂水平低于5×1018 at / cm 3，并且与低掺杂部分接触高度 掺杂部分的长度在1个单层和20纳米之间，并且n型掺杂元素的掺杂水平高于5×1018 at / cm3。

公开(公告)号：US11776564B2

公开(公告)日：2023-10-03

申请号：US17645663

申请日：2021-12-22

Applicant: IMEC vzw

Inventor： Maarten Rosmeulen ,  Arnaud Furnemont ,  Devin Verreck ,  Antonio Arreghini ,  Willem Van Roy ,  Kherim Willems

IPC: G11B3/00

CPC classification number: G11B3/008

Abstract: A memory device including at least one channel and a fluid including particles is provided. In one aspect, the channel includes a least some of the fluid. The memory device may further include an actuator configured to induce a movement of the particles in the channel; and a writing element configured to arrange the particles in a sequence, thereby yielding a sequence of particles in the channel. The particles may include first particles and second particles. The particles may be in a first state or a second state in the channel. In certain aspects, the channel is configured to preserve the sequence of the particles. The memory device may further include a reading element for detecting the sequence of the particles in the channel.

公开(公告)号：US10211287B2

公开(公告)日：2019-02-19

申请号：US14880667

申请日：2015-10-12

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU Leuven R&D

Inventor： Devin Verreck ,  Anne S. Verhulst

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/36 ,  H01L29/739

Abstract: A p-type Tunnel Field-Effect Transistor comprises a drain p-type semiconductor region, a source n-type semiconductor region, and at least one gate stack. The source n-type semiconductor region comprises a lowly doped section with a length of at least 10 nm and with a doping level of n-type dopant elements below 5×1018 at/cm3 and, in contact with the lowly doped section, a highly doped section with a length between 1 monolayer and 20 nm and with a doping level of n-type dopant elements above 5×1018 at/cm3.

公开(公告)号：US20240112737A1

公开(公告)日：2024-04-04

申请号：US18477456

申请日：2023-09-28

Applicant: IMEC VZW

Inventor： Devin Verreck ,  Maarten Rosmeulen

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/16 ,  G11C2216/02

Abstract: This disclosed technology relates to a programmable NAND flash memory and a method for operating the NAND flash memory. The method comprises applying a first voltage to the first gate and a pass voltage to one or more word lines to allow charge to inject into the channel layer and form charge packets. Each charge packet can be arranged next to one of the second gates. The method further comprises applying a programming voltage to the word lines to move the charge packets from the channel layer into the memory cells associated with the second gates next to which they are arranged.

公开(公告)号：US09704992B2

公开(公告)日：2017-07-11

申请号：US15337728

申请日：2016-10-28

Applicant: IMEC VZW

Inventor： Anne Verhulst ,  Devin Verreck ,  AliReza Alian

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/36 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/41775 ,  H01L29/4234 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/7831

Abstract: A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.

公开(公告)号：US20170170314A1

公开(公告)日：2017-06-15

申请号：US15337728

申请日：2016-10-28

Applicant: IMEC VZW

Inventor： Anne Verhulst ,  Devin Verreck ,  AliReza Alian

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/36

CPC classification number: H01L29/7835 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/41775 ,  H01L29/4234 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/7831

Abstract: A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.