Self-Aligning Pick-up Head and Method for Manufacturing a Device with the Self-Aligning Pick-up Head
    1.
    发明申请
    Self-Aligning Pick-up Head and Method for Manufacturing a Device with the Self-Aligning Pick-up Head 有权
    自对准拾取头和用于制造具有自对准拾取头的装置的方法

    公开(公告)号:US20140174652A1

    公开(公告)日:2014-06-26

    申请号:US13722834

    申请日:2012-12-20

    CPC classification number: B25J15/0616 H01L21/67132 H01L21/6838 Y10T29/494

    Abstract: A self-aligning pick-up head, a method to manufacture a pick-up head and a method of manufacturing a device are disclosed. In one embodiment a pick-up head includes a nozzle having a first end portion and a second end portion and a base tool comprising a collet head, wherein the first end portion of the nozzle is gimbaled to the base tool.

    Abstract translation: 公开了一种自动调心拾取头,制造拾取头的方法和制造装置的方法。 在一个实施例中,拾取头包括具有第一端部部分和第二端部部分的喷嘴以及包括夹头的基部工具,其中喷嘴的第一端部被平衡到基部工具。

    Method for testing semiconductor chips or semiconductor chip modules
    2.
    发明授权
    Method for testing semiconductor chips or semiconductor chip modules 有权
    测试半导体芯片或半导体芯片模块的方法

    公开(公告)号:US09395404B2

    公开(公告)日:2016-07-19

    申请号:US13715990

    申请日:2012-12-14

    CPC classification number: G01R31/2601

    Abstract: A semiconductor chip panel includes a plurality of semiconductor chips embedded in an encapsulation material. At least part of the semiconductor chips comprise a first electrical contact element on a first main face and a second electrical contact element on a second main opposite to the first main face, respectively. One of the plurality of semiconductor chips is tested by establishing an electrical contact between a test contact device and the first electrical contact element and between an electrically conductive holder and the second contact element.

    Abstract translation: 半导体芯片面板包括嵌入在封装材料中的多个半导体芯片。 半导体芯片的至少一部分分别包括在第一主面上的第一电接触元件和与第一主面相对的第二主体上的第二电接触元件。 通过在测试接触装置和第一电接触元件之间以及在导电保持器和第二接触元件之间建立电接触来测试多个半导体芯片中的一个。

    Method and apparatus for dynamic alignment of semiconductor devices

    公开(公告)号:US10041973B2

    公开(公告)日:2018-08-07

    申请号:US14017358

    申请日:2013-09-04

    Abstract: A semiconductor device is aligned by placing the semiconductor device in a nest between first and second sections of the nest when the nest is in a receiving position in which the first and second sections are spaced further apart from one another than when the nest is in an aligning position. The nest is moved from the receiving position to the aligning position with the semiconductor device in the nest so that the first and second sections are spaced closer to one another and align the semiconductor device in the nest. The semiconductor device is removed from the nest after the semiconductor device is aligned.

    SEMICONDUCTOR ARRANGEMENT, METHOD FOR PRODUCING A SEMICONDUCTOR CHIP
    5.
    发明申请
    SEMICONDUCTOR ARRANGEMENT, METHOD FOR PRODUCING A SEMICONDUCTOR CHIP 有权
    半导体装置,制造半导体芯片的方法

    公开(公告)号:US20160126211A1

    公开(公告)日:2016-05-05

    申请号:US14926258

    申请日:2015-10-29

    Abstract: A semiconductor assembly is described. In accordance with one example of the invention, the semiconductor assembly comprises a semiconductor body, a top main electrode arranged on a top side, a bottom main electrode arranged on an underside, and a control electrode arranged on the top side. The semiconductor assembly further includes a spring element for the pressure contacting of the control electrode with a pressure force generated by the spring element.

    Abstract translation: 描述半导体组件。 根据本发明的一个示例,半导体组件包括半导体主体,布置在顶侧的顶部主电极,设置在下侧的底部主电极和布置在顶侧的控制电极。 半导体组件还包括用于使控制电极与弹簧元件产生的压力的压力接触的弹簧元件。

    Method and Apparatus for Dynamic Alignment of Semiconductor Devices
    7.
    发明申请
    Method and Apparatus for Dynamic Alignment of Semiconductor Devices 审中-公开
    半导体器件动态对准的方法和装置

    公开(公告)号:US20150063969A1

    公开(公告)日:2015-03-05

    申请号:US14017358

    申请日:2013-09-04

    CPC classification number: G01R1/0466 G01R1/0483 H01L24/75 H01L2224/75704

    Abstract: A semiconductor device is aligned by placing the semiconductor device in a nest between first and second sections of the nest when the nest is in a receiving position in which the first and second sections are spaced further apart from one another than when the nest is in an aligning position. The nest is moved from the receiving position to the aligning position with the semiconductor device in the nest so that the first and second sections are spaced closer to one another and align the semiconductor device in the nest. The semiconductor device is removed from the nest after the semiconductor device is aligned.

    Abstract translation: 当巢处于接收位置时,将半导体器件放置在嵌套的第一和第二部分之间的嵌套中,使半导体器件对准,其中第一和第二部分彼此间隔开,比嵌套在 对齐位置。 嵌套从接收位置移动到与嵌套中的半导体器件的对准位置,使得第一和第二部分彼此间隔开并将半导体器件对准在嵌套中。 在半导体器件对准之后,将半导体器件从巢中移除。

    Method for Testing Semiconductor Chips or Semiconductor Chip Modules
    8.
    发明申请
    Method for Testing Semiconductor Chips or Semiconductor Chip Modules 有权
    半导体芯片或半导体芯片模块测试方法

    公开(公告)号:US20140167800A1

    公开(公告)日:2014-06-19

    申请号:US13715990

    申请日:2012-12-14

    CPC classification number: G01R31/2601

    Abstract: A semiconductor chip panel includes a plurality of semiconductor chips embedded in an encapsulation material. At least part of the semiconductor chips comprise a first electrical contact element on a first main face and a second electrical contact element on a second main opposite to the first main face, respectively. One of the plurality of semiconductor chips is tested by establishing an electrical contact between a test contact device and the first electrical contact element and between an electrically conductive holder and the second contact element.

    Abstract translation: 半导体芯片面板包括嵌入在封装材料中的多个半导体芯片。 半导体芯片的至少一部分分别包括在第一主面上的第一电接触元件和与第一主面相对的第二主体上的第二电接触元件。 通过在测试接触装置和第一电接触元件之间以及在导电保持器和第二接触元件之间建立电接触来测试多个半导体芯片中的一个。

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