公开(公告)号：US20170097782A1

公开(公告)日：2017-04-06

申请号：US14875160

申请日：2015-10-05

Applicant: INTEL CORPORATION

Inventor： ANAND S. RAMALINGAM

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/0246

Abstract: Techniques are disclosed for write suppression to improve endurance rating of non-volatile memories, such as QLC-NAND SSDs or other relatively slow, low endurance non-volatile memories. In an embodiment, an SSD is configured with a fast frontend non-volatile memory, a relatively slow lower endurance backend non-volatile memory, and a frontend manager that selectively transfers data from the fast memory to the slow memory based on transfer criteria. In operation, write data from the host is initially written to the fast memory by the frontend manager. The data is moved from the fast memory to the slow memory in bands. For each data band stored in the fast memory, the frontend manager tracks invalid data counts and data age. Only bands that still remain valid are transferred to the slow memory. After a given band has been fully transferred, it is erased and re-usable for other incoming writes by the frontend manager.

公开(公告)号：US20190235767A1

公开(公告)日：2019-08-01

申请号：US16186636

申请日：2018-11-12

Applicant: INTEL CORPORATION

Inventor： ANAND S. RAMALINGAM

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/0246

Abstract: Techniques are disclosed for write suppression to improve endurance rating of non-volatile memories, such as QLC-NAND SSDs or other relatively slow, low endurance non-volatile memories. In an embodiment, an SSD is configured with a fast frontend non-volatile memory, a relatively slow lower endurance backend non-volatile memory, and a frontend manager that selectively transfers data from the fast memory to the slow memory based on transfer criteria. In operation, write data from the host is initially written to the fast memory by the frontend manager. The data is moved from the fast memory to the slow memory in bands. For each data band stored in the fast memory, the frontend manager tracks invalid data counts and data age. Only bands that still remain valid are transferred to the slow memory. After a given band has been fully transferred, it is erased and re-usable for other incoming writes by the frontend manager.

公开(公告)号：US20170068482A1

公开(公告)日：2017-03-09

申请号：US14846102

申请日：2015-09-04

Applicant: INTEL CORPORATION

Inventor： ANAND S. RAMALINGAM ,  DALE J. JUENEMANN ,  PRANAV KALAVADE

IPC: G06F3/06 ,  G06F12/08 ,  G11C11/56

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0685 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/225 ,  G06F2212/261 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C2211/5648

Abstract: Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.

Abstract translation: 公开了用于对诸如固态驱动器之类的存储器件进行编程的技术。 在一个实施例中，存储器控制器被配置为执行对相邻字线进行粗调和微调步骤的编程序列。 在一个示例中，三个连续的字线被编程为六个步骤。 在步骤1中，字线n被粗略地编程到中间电压电平; 在步骤2，字线n + 1被粗略地编程到中间电压电平; 在步骤3中，字线n被精细地编程到其目标电压电平; 在步骤4，字线n + 2被粗略地编程到中间电压电平; 在步骤5中，字线n + 1被精细地编程到其目标电压电平; 在步骤6，字线n + 2被精细地编程到其目标电压电平。 在所有单元格级别都被编程之前，不允许读取。 相变存储器可用作分段缓冲器。

公开(公告)号：US20160085959A1

公开(公告)日：2016-03-24

申请号：US14492168

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： SANJEEV N. TRIKA ,  JASON COX ,  ANAND S. RAMALINGAM

IPC: G06F21/44 ,  G06F21/31 ,  H04L9/32

CPC classification number: G06F21/44 ,  G06F21/31 ,  G06F21/85 ,  G06F2221/2103 ,  H04L9/0894 ,  H04L9/3271

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for prevention of cable swap security attacks on storage devices. A host system may include a provisioning module configured to generate a challenge-response verification key-pair and further to provide the key-pair to the storage device to enable the challenge-response verification. The system may also include a link error detection module to detect a link error between the host system and the storage device. The system may further include a challenge-response protocol module configured to initiate, in response to the link-error detection, a verification challenge from the storage system and to provide a response to the verification challenge based on the key-pair.

Abstract translation: 通常，本公开提供用于防止对存储设备的电缆交换安全攻击的系统，设备，方法和计算机可读介质。 主机系统可以包括配置模块，配置成生成质询响应验证密钥对，并且进一步将密钥对提供给存储设备以启用挑战响应验证。 该系统还可以包括用于检测主机系统和存储设备之间的链路错误的链路错误检测模块。 所述系统还可以包括质询响应协议模块，所述询问响应协议模块被配置为响应于所述链路错误检测，发起来自所述存储系统的验证挑战并且基于所述密钥对来提供对所述验证挑战的响应。