公开(公告)号：US20190102565A1

公开(公告)日：2019-04-04

申请号：US15721554

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： JAMES A. BOYD ,  DALE J. JUENEMANN ,  ROBERT J. ROYER, JR.

IPC: G06F21/60 ,  G06F3/06 ,  G06F17/30

Abstract: Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.

公开(公告)号：US20170068482A1

公开(公告)日：2017-03-09

申请号：US14846102

申请日：2015-09-04

Applicant: INTEL CORPORATION

Inventor： ANAND S. RAMALINGAM ,  DALE J. JUENEMANN ,  PRANAV KALAVADE

IPC: G06F3/06 ,  G06F12/08 ,  G11C11/56

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0685 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/225 ,  G06F2212/261 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C2211/5648

Abstract: Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.

Abstract translation: 公开了用于对诸如固态驱动器之类的存储器件进行编程的技术。 在一个实施例中，存储器控制器被配置为执行对相邻字线进行粗调和微调步骤的编程序列。 在一个示例中，三个连续的字线被编程为六个步骤。 在步骤1中，字线n被粗略地编程到中间电压电平; 在步骤2，字线n + 1被粗略地编程到中间电压电平; 在步骤3中，字线n被精细地编程到其目标电压电平; 在步骤4，字线n + 2被粗略地编程到中间电压电平; 在步骤5中，字线n + 1被精细地编程到其目标电压电平; 在步骤6，字线n + 2被精细地编程到其目标电压电平。 在所有单元格级别都被编程之前，不允许读取。 相变存储器可用作分段缓冲器。