公开(公告)号：US09495103B2

公开(公告)日：2016-11-15

申请号：US14580976

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F3/00

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US09058111B2

公开(公告)日：2015-06-16

申请号：US14581011

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F3/06 ,  G06F3/00 ,  G06F13/38

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract translation: 提供了一种用于对存储器模块进行编程以启动训练模式的装置和计算机可读存储介质，其中存储器模块在总线接口的边带通道上发送连续位模式; 通过总线接口接收位模式; 从接收到的位模式确定位模式中的值的转变以确定所确定的值的转换之间的数据眼; 以及确定设置以控制相位内插器以产生用于对所确定的数据眼睛内的数据进行采样的内插信号。

公开(公告)号：US10482041B2

公开(公告)日：2019-11-19

申请号：US15294671

申请日：2016-10-14

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F3/06 ,  G06F13/38 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US09766817B2

公开(公告)日：2017-09-19

申请号：US14580869

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US09021154B2

公开(公告)日：2015-04-28

申请号：US14040548

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F13/28 ,  G11C7/10 ,  G06F13/16 ,  G06F13/00

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US10331585B2

公开(公告)日：2019-06-25

申请号：US15624702

申请日：2017-06-15

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F13/38 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.