公开(公告)号：US10795755B2

公开(公告)日：2020-10-06

申请号：US15080577

申请日：2016-03-24

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  Jonathan C. Jasper ,  Murugasamy K. Nachimuthu ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for performing error handling operations using error signals A first error signal is asserted on an error pin on a bus to signal to a host memory controller that error handling operations are being performed by a memory module controller in response to detecting an error. Error handling operations are performed to return the bus to an initial state in response to detecting the error. A second error signal is asserted on the error pin on the bus to signal that error handling operations have completed and the bus is returned to the initial state.

公开(公告)号：US09025399B1

公开(公告)日：2015-05-05

申请号：US14099315

申请日：2013-12-06

Applicant: Intel Corporation

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  John V. Lovelace ,  Benjamin T. Tyson

IPC: G11C7/22

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory controller transmits a control signal to a memory module, where the memory controller continuously transmits a clock signal to the memory module. The memory controller determines adjustments to the control signal with respect to the clock signal, by iteratively analyzing a strobe signal.

Abstract translation: 存储器控制器将控制信号发送到存储器模块，其中存储器控制器将时钟信号连续发送到存储器模块。 存储器控制器通过迭代地分析选通信号来确定相对于时钟信号对控制信号的调整。

公开(公告)号：US10331585B2

公开(公告)日：2019-06-25

申请号：US15624702

申请日：2017-06-15

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F13/38 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US09627029B2

公开(公告)日：2017-04-18

申请号：US14639025

申请日：2015-03-04

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  John V. Lovelace ,  Benjamin T. Tyson

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory controller transmits a control signal to a memory module, where the memory controller continuously transmits a clock signal to the memory module. The memory controller determines adjustments to the control signal with respect to the clock signal, by iteratively analyzing a strobe signal.

公开(公告)号：US10482041B2

公开(公告)日：2019-11-19

申请号：US15294671

申请日：2016-10-14

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F3/06 ,  G06F13/38 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US09766817B2

公开(公告)日：2017-09-19

申请号：US14580869

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US09021154B2

公开(公告)日：2015-04-28

申请号：US14040548

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F13/28 ,  G11C7/10 ,  G06F13/16 ,  G06F13/00

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US09495103B2

公开(公告)日：2016-11-15

申请号：US14580976

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F3/00

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US09229828B2

公开(公告)日：2016-01-05

申请号：US14563761

申请日：2014-12-08

Applicant: INTEL CORPORATION

Inventor： Dableena Das ,  Kai Cheng ,  Jonathan C. Jasper

IPC: H03M13/05 ,  G06F11/10 ,  G06F11/20

CPC classification number: G06F11/2094 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/05

Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Abstract translation: 描述了根据本发明的一个实施例的用于实现高存储器可靠性，可用性和可服务性（RAS）的机制。 本发明的实施例的方法包括：检测在计算系统处的存储器系统的第一通道的多个存储器件的第一存储器件的永久故障，并通过合并第一纠错码来消除第一故障（ ECC）具有第二信道的第二ECC定位器装置的第一信道的定位装置，其中在第二信道执行合并。

公开(公告)号：US09058111B2

公开(公告)日：2015-06-16

申请号：US14581011

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  Arnaud J. Forestier

IPC: G06F3/06 ,  G06F3/00 ,  G06F13/38

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract translation: 提供了一种用于对存储器模块进行编程以启动训练模式的装置和计算机可读存储介质，其中存储器模块在总线接口的边带通道上发送连续位模式; 通过总线接口接收位模式; 从接收到的位模式确定位模式中的值的转变以确定所确定的值的转换之间的数据眼; 以及确定设置以控制相位内插器以产生用于对所确定的数据眼睛内的数据进行采样的内插信号。