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    Enumerated per device addressability for memory subsystems
    1.
    发明授权
    Enumerated per device addressability for memory subsystems 有权

    公开(公告)号：US10997096B2

    公开(公告)日：2021-05-04

    申请号：US15987854

    申请日：2018-05-23

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  Bill Nale

    IPC: G06F13/16 ,  G06F3/06 ,  G06F9/30 ,  G06F12/02 ,  G06F1/26

    Abstract: A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or buffer devices that share an enable line. The system includes a host and multiple memory devices that can be coupled over a command bus and a data bus. The devices include a configuration or mode register to store a value to indicate whether PDA enumeration is enabled. When enabled, the host can provide an enumeration identifier (ID) command via the command bus with a signal via the data bus to assign an enumeration ID. After assignment of the enumeration ID, the host can send PDA commands via the command bus with the enumeration ID, without a signal on the data bus. Devices only process PDA commands that match their assigned enumeration ID, enabling the setting of device-specific configuration settings without needing to use the data bus on every PDA command.

    Efficiently training memory device chip select control
    2.
    发明授权
    Efficiently training memory device chip select control 有权

    公开(公告)号：US10416912B2

    公开(公告)日：2019-09-17

    申请号：US15721516

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  Christopher P. Mozak ,  Christopher E. Cox

    IPC: G06F3/06 ,  G11C11/4076 ,  G11C8/12 ,  G11C29/00 ,  G11C29/02

    Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

    Memory bus MR register programming process
    4.
    发明授权
    Memory bus MR register programming process 有权

    公开(公告)号：US10891243B2

    公开(公告)日：2021-01-12

    申请号：US16529700

    申请日：2019-08-01

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  John V. Lovelace ,  John R. Goles

    IPC: G06F13/36 ,  G06F13/16 ,  G06F1/10

    Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

    Device, system and method to generate link training signals
    10.
    发明授权
    Device, system and method to generate link training signals 有权

    公开(公告)号：US11435909B2

    公开(公告)日：2022-09-06

    申请号：US16390551

    申请日：2019-04-22

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  Moshe Jacob Finkelstein ,  Ramesh Subashchandrabose ,  Lohit R. Yerva

    IPC: G06F3/06 ,  G06N20/00

    Abstract: Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.

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